Bumpless build-up layer (BBUL) semiconductor package with ultra-thin dielectric layer

Patent metadata

Field	Value
Publication number	US-9520350-B2
Application number	US-201313801859-A
Country	US
Kind code	B2
Filing date	Mar 13, 2013
Priority date	Mar 13, 2013
Publication date	Dec 13, 2016
Grant date	Dec 13, 2016

Abstract

Bumpless build-up layer (BBUL) semiconductor packages with ultra-thin dielectric layers are described. For example, an apparatus includes a semiconductor die including an integrated circuit having a plurality of external conductive bumps. A semiconductor package houses the semiconductor die. The semiconductor package includes a dielectric layer disposed above the plurality of external conductive bumps. A conductive via is disposed in the dielectric layer and coupled to one of the plurality of conductive bumps. A conductive line is disposed on the dielectric layer and coupled to the conductive via.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a layer comprising a pattern of spaced apart conductive lines;
a first dielectric layer disposed on and between the conductive lines of the pattern of spaced apart conductive lines;
a second dielectric layer disposed above the first dielectric layer;
a conductive via disposed in the first dielectric layer;
a conductive routing line disposed in the second dielectric layer and coupled to the conductive via; and
a patterned titanium nitride layer disposed directly between the first and second dielectric layers, wherein the conductive via is disposed in the patterned titanium nitride layer, and the conductive routing line is disposed on the patterned titanium nitride layer.

2. The semiconductor package of claim 1 , wherein the first and second dielectric layers are substrate dielectric build-up layers.

3. The semiconductor package of claim 2 , wherein the first and second dielectric layers are non-photo-definable substrate dielectric build-up layers.

4. The semiconductor package of claim 2 , wherein the first dielectric layer is a non-photo-definable substrate dielectric build-up layer, and the second dielectric layer is a photo-definable substrate dielectric build-up layer.

5. The semiconductor package of claim 2 , wherein the first dielectric layer is a photo-definable substrate dielectric build-up layer, and the second dielectric layer is a non-photo-definable substrate dielectric build-up layer.

6. The semiconductor package of claim 2 , wherein the first and second dielectric layers are photo-definable substrate dielectric build-up layers.

7. The semiconductor package of claim 1 , further comprising:
a silicon nitride layer disposed on the conductive routing line and on exposed portions of the second dielectric layer.

8. The semiconductor package of claim 1 , wherein the pattern of spaced apart conductive lines has a fine line spacing (FLS) of less than 8 micron/8 micron FLS.

9. The semiconductor package of claim 1 , wherein the pattern of spaced apart conductive lines, the conductive via, and the conductive routing line all comprise copper.

10. An apparatus, comprising:
a semiconductor die comprising an integrated circuit having a plurality of external electrical contacts; and
a semiconductor package housing the semiconductor die, the semiconductor package comprising:
a layer comprising a pattern of spaced apart conductive lines coupled to the plurality of external contacts of the semiconductor die;
a first dielectric layer disposed on and between the conductive lines of the pattern of spaced apart conductive lines;
a second dielectric layer disposed above the first dielectric layer;
a conductive via disposed in the first dielectric layer;
a conductive routing line disposed in the second dielectric layer and coupled to the conductive via; and
a patterned titanium nitride layer disposed directly between the first and second dielectric layers, wherein the conductive via is disposed in the patterned titanium nitride layer, and the conductive routing line is disposed on the patterned titanium nitride layer.

11. The apparatus of claim 10 , wherein the plurality of external electrical contacts is a plurality of external bumps.

12. The apparatus of claim 10 , wherein the first and second dielectric layers of the semiconductor package are substrate dielectric build-up layers.

13. The apparatus of claim 12 , wherein one or both of the first and second dielectric layers is a photo-definable substrate dielectric build-up layer.

14. The apparatus of claim 10 , the semiconductor package further comprising:
a second silicon nitride layer disposed on the conductive routing line and on exposed portions of the second dielectric layer.

15. The apparatus of claim 10 , wherein the pattern of spaced apart conductive lines of the semiconductor package has a fine line spacing (FLS) of less than 8 micron/8 micron FLS.

Assignees

• Teh Weng Hong
• Davies-Venn Emile
• Andideh Ebrahim
• Raorane Digvijay A
• Sobieski Daniel N
• Intel Corp

Inventors

• Teh Weng Hong
• Davies-Venn Emile
• Andideh Ebrahim
• Raorane Digvijay A
• Sobieski Daniel N

Classifications

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W72/241

  Dispositions, e.g. layouts · CPC title

• H10W70/09

  extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs · CPC title

• H10W20/0884

  involving forming vias by burying sacrificial pillars in the dielectric parts and removing the pillars · CPC title

• H10W20/086

  involving buried masks · CPC title