Multiple storage devices implemented using a common connector

Patent metadata

Field	Value
Publication number	US-10509759-B2
Application number	US-201715476882-A
Country	US
Kind code	B2
Filing date	Mar 31, 2017
Priority date	Mar 31, 2017
Publication date	Dec 17, 2019
Grant date	Dec 17, 2019

Abstract

Provided are an apparatus, system, and method relating to detecting, during a system boot operation, whether a device arranged to implement a first bus interface protocol is coupled to a system through a connector. A bus clock is programmed to be off in response to detection of no device implementing the first bus interface protocol being coupled to the system through the connector. After the bus clock is programmed to be off, a buffer is reprogrammed to assume that the connector implements a second bus interface protocol coupled to a storage device. After reprogramming the buffer, the apparatus, system, and method detect whether a device arranged to implement the second bus interface protocol is coupled to the connector, and the device arranged to implement the second bus interface protocol is initialized in response to detection that the device is coupled to the connector. Other embodiments are described and claimed.

First claim

What is claimed:

1. A method, comprising:
detecting, during a system boot operation, whether a device implementing a first bus interface protocol is coupled to a bus in the system through a connector, wherein the detecting includes evaluating a group comprising a plurality of lanes of the bus;
determining whether the device implementing the first bus interface protocol is a storage device implementing a logical device interface protocol in response to detecting that the device implementing the first bus interface protocol is coupled to the system through the connector;
initializing the device as a storage device to communicate on the bus in response to determining that the device is a storage device implementing a logical device interface protocol;
initializing the device implementing the first bus interface protocol to communicate on the bus in response to determining that the device is not a storage device implementing a logical device interface protocol;
programming a bus clock to the connector to be off in response to detecting that no device implementing the first bus interface protocol is coupled to the bus in the system through the connector;
after programming the bus clock to be off, reprogramming a buffer to connect to a device implementing a second bus interface protocol to couple a device;
after reprogramming the buffer, detecting whether a device implementing the second bus interface protocol is coupled to the bus in the system through the connector; and
initializing the device implementing the second bus interface protocol in response to detecting that the device implementing the second bus interface protocol is coupled to the bus in the system through the connector.

2. The method of claim 1 , wherein the first bus interface protocol comprises a Peripheral Component Interconnect Express (PCIe) bus interface protocol, and the second bus interface protocol comprises a Serial Advanced Technology Attachment (SATA) bus interface protocol.

3. The method of claim 1 , wherein the group comprising a plurality of lanes of the bus comprises a four lane high speed input output (HSIO) group.

4. The method of claim 3 , wherein reprogramming the buffer includes reprogramming the buffer on four ports.

5. The method of claim 4 , further comprising turning off any unused buffer after the initializing the device implementing the second bus interface protocol in response to detecting that the device implementing the second bus interface protocol is coupled to the bus in the system through the connector.

6. The method of claim 1 , wherein the first bus interface protocol comprises a Peripheral Component Interconnect Express (PCIe) bus interface protocol, wherein the second bus interface protocol comprises a Serial Advanced Technology Attachment (SATA) bus interface protocol, and wherein the logical device interface protocol comprises a Non-Volatile Memory Express (NVMe) logical device bus interface protocol.

7. The method of claim 6 , wherein the group comprising a plurality of lanes of the bus comprises a four lane high speed input output (HSIO) group.

8. The method of claim 7 , further comprising, after initializing the storage device in response to determining that the device implementing the first bus interface protocol also implements a logical device interface protocol, reprogramming any unused HSIO buffers to assume that the connector implements the second bus interface protocol.

9. The method of claim 1 , wherein the initializing the device implementing the second bus interface protocol in response to detecting that the device implementing the second bus interface protocol is coupled to the bus in the system through the connector comprises initializing a plurality of SATA drives.

10. An apparatus comprising:
initialization logic in communication with a bus, a bus clock, a buffer, a connector, and a storage device, at least a portion of the initialization logic in hardware, the initialization logic to:
detect whether a device arranged to implement a first bus interface protocol is coupled to the bus through the connector, wherein the detection includes evaluation of a group comprising a plurality of lanes of the bus;
determine whether the device arranged to implement the first bus interface protocol is a storage device arranged to implement a logical device interface protocol in response to detection of the device arranged to implement the first bus interface protocol is coupled to the bus through the connector;
initialize the device as a storage device to communicate on the bus in response to the determination that the device is a storage device implementing a logical device interface protocol;
initialize the device implementing the first bus interface protocol to communicate on the bus in response to a determination that the device is not a storage device implementing a logical device interface protocol;
program a bus clock to the connector to be off in response to detection of no device arranged to implement the first bus interface protocol is coupled through the connector;
after the bus clock is programmed to be off, reprogram a buffer to connect to a device that implements a second bus interface protocol to the bus to couple a device to the bus through the connector;
after the buffer is reprogrammed, detect whether a device arranged to implement the second bus interface protocol is coupled to the connector; and
initialize the device arranged to implement the second bus interface protocol in response to detection that a device arranged to implement the second bus interface protocol is coupled to the connector.

11. The apparatus of claim 10 , wherein the first bus interface protocol comprises a Peripheral Component Interconnect Express (PCIe) bus interface protocol, and the second bus interface protocol comprises a Serial Advanced Technology Attachment (SATA) bus interface protocol.

12. The apparatus of claim 10 , wherein group comprising a plurality of lanes of the bus comprises a four lane high speed input output (HSIO) group.

13. The apparatus of claim 10 , wherein the first bus interface protocol comprises a Peripheral Component Interconnect Express (PCIe) bus interface protocol, wherein the second bus interface protocol comprises a Serial Advanced Technology Attachment (SATA) bus interface protocol, and wherein the logical device interface protocol comprises a Non-Volatile Memory Express (NVMe) logical device bus interface protocol.

14. The apparatus of claim 13 , wherein the group comprising a plurality of lanes of the bus comprises a four lane high speed input output (HSIO) group.

15. The apparatus of claim 14 , wherein the initialization logic, after the initialization of the storage device in response to the determination that the device arranged to implement the first bus interface protocol also implements a logical device interface protocol, reprograms any unused HSIO buffers to cause the connector to implement the second bus interface protocol.

16. The apparatus of claim 10 , wherein the initialization logic that is configured to initialize the device arranged to implement the second bus interface protocol in response to detection that a device arranged to implement the second bus interface protocol is coupled to the connector, is configured to initialize a plurality of SATA drives.

17. A system comprising:
a bus;
a bus clock in communication with the bus;
a buffer in communication with the bus;
a storage device for storing data;
a connector configured to couple the storage device to the bus;
initialization logic to:
detect whether a device arra

Assignees

• Intel Corp

Inventors

• Willis Daniel S
• Constantine Anthony M

Classifications

• G06F13/4234

  being a memory bus · CPC title

• G06F13/4221 Primary

  being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus · CPC title

• G06F2213/0026

  PCI express · CPC title

• G06F13/385

  for adaptation of a particular data processing system to different peripheral devices · CPC title

• G06F13/4291

  using a clocked protocol · CPC title