Synchronization of electronic device with another electronic device on bus using synchronization field

Patent metadata

Field	Value
Publication number	US-2016147686-A1
Application number	US-201615011158-A
Country	US
Kind code	A1
Filing date	Jan 29, 2016
Priority date	Jun 1, 2012
Publication date	May 26, 2016
Grant date	—

Abstract

Various embodiments are described herein related to techniques for synchronizing a slave device to a master device that communicates using a unified bus communication protocol or some aspect thereof. In one example, the method may comprise assuming a first mode of operation for the unified bus communication protocol; searching for a synchronization pattern at one or more locations in transmitted data according to the first mode of operation; obtaining synchronization when the located synchronization pattern is verified according to at least one synchronization rule for the mode of operation; and if synchronization is not obtained based on the assumed first mode of operation, a second mode of operation for the unified bus communication protocol is assumed and the searching and obtaining acts are carried out on the transmitted data according to the second mode of operation.

First claim

What is claimed is:

1 . A method of synchronizing a slave device to a master device on a bus using a synchronization field, the method comprising:
receiving a bitstream of data on the bus, the bitstream comprising occurrences of the synchronization field, the synchronization field comprising a constant sync field and a dynamic sync field, the constant sync field having a constant sync value; locating a first occurrence of the synchronization field in the received bitstream by searching for the constant sync value of the constant sync field; reading a first value of the dynamic sync field of the located first occurrence of the synchronization field; based on the first value computing an expected value of the dynamic sync field of a next occurrence of the synchronization field; locating the next occurrence of the synchronization field by searching again for the constant sync value of the constant sync field in the bitstream; reading a second value of the dynamic sync field of the located next occurrence of the synchronization field; and verifying that the second value is equal to the computed expected value.

2 . The method of claim 1 , wherein the dynamic sync field is 4 bits in length.

3 . The method of claim 1 , wherein the constant sync value comprises the bit string “10110001”.

4 . The method of claim 2 , wherein when the first value is represented in MSB (Most Significant Bit) first order as {S4, S3, S2, S1}, then the expected value of the dynamic sync field of the next occurrence of the synchronization field in MSB first order is {S3, S2, 51, (S4 XOR S3)}, where XOR is the “exclusive or” operation.

5 . A method of enabling synchronization of slave devices to a master device on a bus using a synchronization field, the synchronization field comprising a constant sync field and a dynamic sync field, the constant sync field having a constant sync value, the method comprising:
transmitting, by the master device, in a first frame within a bitstream of data on the bus, a first instance of the synchronization field, the dynamic sync field of the first instance having a first dynamic sync value; and transmitting, by the master device, in a second frame within the bitstream, the second frame being successive to the first frame, a second instance of the synchronization field, the dynamic sync field of the second instance having a second dynamic sync value, wherein the second dynamic sync value can be determined from the first dynamic sync value.

6 . The method of claim 5 , wherein the dynamic sync field is 4 bits in length.

7 . The method of claim 5 , wherein the constant sync value comprises the bit string “10110001”.

8 . The method of claim 6 , wherein a first time the synchronization field is transmitted after reset the master device sets the dynamic sync field to a value of “1111”.

9 . The method of claim 6 , wherein when the first dynamic sync value is represented in MSB (Most Significant Bit) first order as {S4, S3, S2, S1}, the second dynamic sync value in MSB first order is {S3, S2, 51, S4 XOR S3}, where XOR is the “exclusive or” operation.

10 . An electronic device that synchronizes with another electronic device on a bus using a synchronization field, the electronic device comprising:
a memory storing executable instructions; and a processor in communication with the memory configured to execute the instructions to cause the device to:
receive a bitstream of data on the bus, the bitstream comprising occurrences of the synchronization field, the synchronization field comprising a constant sync field and a dynamic sync field, the constant sync field having a constant sync value;
locate a first occurrence of the synchronization field in the received bitstream by searching for the constant sync value of the constant sync field;
read a first value of the dynamic sync field of the located first occurrence of the synchronization field;
based on the first value compute an expected value of the dynamic sync field of a next occurrence of the synchronization field;
locate the next occurrence of the synchronization field by searching again for the constant sync value of the constant sync field in the bitstream;
read a second value of the dynamic sync field of the located next occurrence of the synchronization field; and
verify that the second value is equal to the computed expected value.

11 . The device of claim 10 , wherein the dynamic sync field is 4 bits in length.

12 . The device of claim 10 , wherein the constant sync value comprises the bit string “10110001”.

13 . The device of claim 11 , wherein when the first value is represented in MSB (Most Significant Bit) first order as {S4, S3, S2, S1}, then the expected value of the dynamic sync field of the next occurrence of the synchronization field in MSB first order is {S3, S2, 51, (S4 XOR S3)}, where XOR is the “exclusive or” operation.

14 . An electronic device that synchronizes with another electronic device on a bus using a synchronization field, the synchronization field comprising a constant sync field and a dynamic sync field, the constant sync field having a constant sync value, the electronic device comprising:
a memory storing executable instructions; and a processor in communication with the memory configured to execute the instructions to cause the device to:
transmit in a first frame within a bitstream of data on the bus a first instance of the synchronization field, the dynamic sync field of the first instance having a first dynamic sync value; and
transmit in a second frame within the bitstream, the second frame being successive to the first frame, a second instance of the synchronization field, the dynamic sync field of the second instance having a second dynamic sync value, wherein the second dynamic sync value can be determined from the first dynamic sync value.

15 . The device of claim 14 , wherein the dynamic sync field is 4 bits in length.

16 . The device of claim 14 , wherein the constant sync value comprises the bit string “10110001”.

17 . The device of claim 15 , wherein the processor is further configured to cause the device to set the dynamic sync field to “1111” a first time that the synchronization field is transmitted after reset.

18 . The device of claim 15 , wherein when the first dynamic sync value is represented in MSB (Most Significant Bit) first order as {S4, S3, S2, S1}, the second dynamic sync value in MSB first order is {S3, S2, 51, S4 XOR S3}, where XOR is the “exclusive or” operation.

19 . A non-transitory computer readable medium comprising instructions executable on a processor of an electronic device that synchronizes to another electronic device on a bus using a synchronization field, the instructions causing the processor to execute a method comprising:
receiving a bitstream of data on the bus, the bitstream comprising occurrences of the synchronization field, the synchronization field comprising a constant sync field and a dynamic sync field, the constant sync field having a constant sync value; locating a first occurrence of the synchronization field in the received bitstream by searching for the constant sync value of the constant sync field; reading a first value of the dynamic sync field of the located first occurrence of the synchronization field; based on the first value computing an expected value of the dynamic sync field of a next occurrence of the synchronization field; locating the next occurrence of the synchronization field by searching again for the constant sync value

Assignees

• Blackberry Ltd

Inventors

• Poulsen Jens Kristian

Classifications

• G06F1/12

  Synchronisation of different clock signals {provided by a plurality of clock generators} · CPC title

• G06F13/3625 Primary

  using a time dependent access · CPC title

• H04L7/048

  using the properties of error detecting or error correcting codes, e.g. parity as synchronisation signal · CPC title

• H04L1/24

  Testing correct operation · CPC title

• H04L7/10

  Arrangements for initial synchronisation · CPC title