Methods and apparatus for sharing a network interface controller

Patent metadata

Field	Value
Publication number	US-9280504-B2
Application number	US-201213593591-A
Country	US
Kind code	B2
Filing date	Aug 24, 2012
Priority date	Aug 24, 2012
Publication date	Mar 8, 2016
Grant date	Mar 8, 2016

Abstract

Methods, apparatus, and systems for enhancing communication between compute resources and networks in a micro-server environment. Micro-server modules configured to be installed in a server chassis include a plurality of processor subsystems coupled in communication to a shared Network Interface Controller (NIC) via PCIe links. The shared NIC includes at least one Ethernet port and a PCIe block including a shared PCIe interface having a first number of lanes. The PCIe lines between the processor sub-systems and the shared PCIe interface employ a number of lanes that is less than the first number of lanes, and during operation of the micro-server module, the shared NIC is configured to enable each processor sub-system to access the at least one Ethernet port using the PCIe link between that processor sub-system and the shared PCIe block on the shared NIC.

First claim

What is claimed is:

1. A micro-server module, comprising:
a printed circuit board (PCB), having a connector and plurality of components mounted thereon or operatively coupled thereto interconnected via wiring on the PCB, the components including,
a plurality of processor sub-systems, each including a processor coupled to memory and including at least one PCIe (Peripheral Component Interconnect Express) interface and configured to be logically implemented as a micro-server; and
a shared Network Interface Controller (NIC), including at least one Ethernet port and a PCIe block including a shared PCIe interface having a first number of lanes,
wherein the PCB includes wiring for facilitating a PCIe link between a PCIe interface for each processor sub-system and the shared PCIe interface on the shared NIC, each of the PCIe links having a number of lanes that is less than the first number of lanes, and wherein, during operation of the micro-server module, the shared NIC is configured to enable each processor sub-system to access the at least one Ethernet port using the PCIe link between that processor sub-system and the shared PCIe interface on the shared NIC,
wherein the shared PCIe block comprises a multi-layer interface including, for each PCIe link, a PCIe physical (PHY) layer, a link layer, and a transaction layer, and wherein the shared PCIe block further includes a multiple lane PCIe PHY layer and a multiplexer that is configured to multiplex signals from the multiple lane PCIe PHY layer and a PCIe PHY layer associated with a PCIe link to a link layer associated with the PCIe link.

2. The micro-server module of claim 1 , wherein the total number of lanes for the PCIe links equals the first number of lanes.

3. The micro-server module of claim 1 , wherein at least one of the PCIe links employs a single lane.

4. The micro-server module of claim 1 , wherein each of the PCIe links employs a single lane.

5. The micro-server module of claim 1 , wherein each processor sub-system comprises a System on a Chip.

6. The micro-server module of claim 1 , further comprising a Board Management Controller (BMC) coupled to the shared NIC, wherein the shared NIC is configured to provided shared access between the BMC and the plurality of processor sub-systems.

7. The micro-server module of claim 1 , wherein the PCB connector comprises a PCIe edge connector.

8. The micro-server module of claim 1 , wherein the shared NIC includes at least two Ethernet ports and is further configured to support a distributed switching function.

9. The micro-server module of claim 8 , wherein the distributed switching function includes logic for determining whether a packet received at a first Ethernet port is destined for one of the plurality of micro-servers, and if it is not, forwarding the packet out of a second Ethernet port.

10. A micro-server module, comprising:
a printed circuit board (PCB), having a connector and plurality of components mounted thereon or operatively coupled thereto interconnected via wiring on the PCB, the components including,
a plurality of processor sub-systems, each including a processor coupled to memory and including at least one PCIe (Peripheral Component Interconnect Express) interface and configured to be logically implemented as a micro-server; and
a shared Network Interface Controller (NIC), including at least one Ethernet port and a PCIe block including a shared PCIe interface having a first number of lanes,
wherein the PCB includes wiring for facilitating a PCIe link between a PCIe interface for each processor sub-system and the shared PCIe interface on the shared NIC, each of the PCIe links having a number of lanes that is less than the first number of lanes, and wherein, during operation of the micro-server module, the shared NIC is configured to enable each processor sub-system to access the at least one Ethernet port using the PCIe link between that processor sub-system and the shared PCIe interface on the shared NIC,
wherein the shared PCIe block comprises a multi-layer interface including, for each PCIe link, a PCIe physical (PHY) layer, a link layer, and a transaction layer, and wherein the multi-layer interface further comprises a PCI link to function mapping layer and a PCIe function layer including a plurality of PCIe functions.

11. The micro-server module of claim 10 , wherein the multi-layer interface further comprises shared NIC logic layer configured to share access between PCIe functions and Ethernet functions provided by the shared NIC.

12. A micro-server system comprising:
a chassis having at least one of a baseboard, mid-plane, backplane or mezzanine board mounted therein and including a plurality of slots; and
a plurality of micro-server modules, each including a connector configured to mate with a mating connector on one of the baseboard, mid-plane, backplane, or mezzanine board, each micro-server module further including components and circuitry for implementing a plurality of micro-servers, each micro-server including a processor sub-system coupled to a shared Network Interface Controller (NIC) via a PCIe (Peripheral Component Interconnect Express) link, the shared NIC including at least one Ethernet port and a shared PCIe block including a shared PCIe interface having a first number of lanes, each of the PCIe links coupled to the shared PCIe interface and having a number of lanes that is less than the first number of lanes,
wherein the shared PCIe block comprises a multi-layer interface including, for each PCIe link, a PCIe physical (PHY) layer, a link layer, and a transaction layer, and wherein the shared PCIe block further includes a multiple lane PCIe PHY layer and a multiplexer that is configured to multiplex signals from the multiple lane PCIe PHY layer and a PCIe PHY layer associated with a PCIe link to a link layer associated with the PCIe link.

13. The micro-server system of claim 12 , wherein each of the PCIe links employs a single lane.

14. The micro-server system of claim 12 , further comprising at least one Ethernet switch module having a connector configured to mate with a mating connector on one of the baseboard, mid-plane, backplane, or mezzanine board.

15. The micro-server system of claim 12 , wherein the shared NIC for at least one of the plurality of micro-server modules includes at least two Ethernet ports and is further configured to support an Ethernet switching function.

16. The micro-server system of claim 12 , wherein the shared NIC for at least one of the plurality of micro-server modules includes at least two Ethernet ports and is further configured to support a distributed switching function.

17. The micro-server system of claim 16 , wherein the distributed switching function includes logic for determining whether a packet received at a first Ethernet port is destined for one of the plurality of micro-servers on a micro-server module, and if it is not, forwarding the packet out of a second Ethernet port.

18. The micro-server system of claim 16 , wherein the system is configured to support at least one of a ring, torus, and 3D torus distributed switching scheme.

19. A shared Network Interface Controller (NIC), comprising:
a PCIe block including a shared PCIe interface having a first number of lanes;
a plurality of Ethernet ports; and
shared NIC logic, configured, upon operation of the shared NIC, to enable shared access to the plurality of Ethernet ports for components linked in communication with the shared NIC via a plurality of PCIe links coupled to the shared PCIe interface, each of

Assignees

• Ben-Michael Simoni
• Louzoun Eliel
• Intel Corp

Inventors

• Ben-Michael Simoni
• Louzoun Eliel

Classifications

• G06F13/385 Primary

  for adaptation of a particular data processing system to different peripheral devices · CPC title

• G06F13/14

  Handling requests for interconnection or transfer · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title