Peripheral component interconnect express (PCIe) card having multiple PCIe connectors

US9710421B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9710421-B2
Application numberUS-201414569041-A
CountryUS
Kind codeB2
Filing dateDec 12, 2014
Priority dateDec 12, 2014
Publication dateJul 18, 2017
Grant dateJul 18, 2017

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

Some embodiments include apparatus and methods having a circuit board, a device located on the circuit board, a first Peripheral Component Interconnect Express (PCIe) connector located on the circuit board and coupled to the device, and a second PCIe connector located on the circuit board and coupled to the device. The first PCIe connector is arranged to couple to a first connector of an additional circuit board. The second PCIe connector is arranged to couple to a second connector of the additional circuit board.

First claim

Opening claim text (preview).

What is claimed is: 1. An apparatus comprising: a circuit board; a device located on the circuit board; a first Peripheral Component Interconnect Express (PCIe) connector located on the circuit board and coupled to the device, the first PCIe connector arranged to couple to a first connector of an additional circuit board; a second PCIe connector located on the circuit board and coupled to the device, the second PCIe connector arranged to couple to a second connector of the additional circuit board; first conductive contacts arranged to couple the device to a first input/output (I/O) connector of the circuit board; and second conductive contacts arranged to couple the device to a second I/O connector of the circuit board, wherein the first conductive contacts are arranged to conduct signals from a first computer network through the first I/O connector, and the second conductive contacts are arranged to conduct signals from a second computer network through the second I/O connector. 2. The apparatus of claim 1 , wherein the first connector of the additional circuit board includes a first PCIe slot, and the second additional connector of the additional circuit board includes a second PCIe slot. 3. The apparatus of claim 1 , wherein the circuit board includes a first edge and a second edge, the first PCIe connector includes conductors located at the first edge, and the second PCIe connector includes conductors located at the second edge. 4. The apparatus of claim 3 , wherein the first edge is opposite from the second edge. 5. An apparatus comprising: a circuit board; a device located on the circuit board; a first Peripheral Component Interconnect Express (PCIe) connector located on the circuit board and coupled to the device, the first PCIe connector arranged to couple to a first connector of an additional circuit board; and a second PCIe connector located on the circuit board and coupled to the device, the second PCIe connector arranged to couple to a second connector of the additional circuit board, wherein: each of the first and second PCIe connectors includes conductors, the conductors of first PCIe connector include a first group of conductors on a first side of the circuit board, and a second group of conductors on a second side of the circuit board; the conductors of the second PCIe connector include a first group of conductors on the second side of the circuit board, and a second group of conductors on the first side of the circuit board; and the first group of conductors of each of the first and second PCIe connectors is arranged based on PCIe connector pin-out specification for a first side of a printed-circuit-board (PCB), and the second group of conductors of each of the first and second PCIe connectors is arranged based on PCIe connector pin-out specification for a second side of the PCB. 6. The apparatus of claim 5 , wherein the circuit board, the device, and the first and second PCIe connectors are parts of an expansion card. 7. The apparatus of claim 6 , wherein the expansion card includes one of a host adapter device, a network interface controller (NIC) device, or a converged network adapter device. 8. The apparatus of claim 6 , wherein the expansion card conforms to a PCIe form factor. 9. An apparatus comprising: a circuit board; a device located on the circuit board; a first Peripheral Component Interconnect Express (PCIe) connector located on the circuit board and coupled to the device, the first PCIe connector arranged to couple to a first connector of an additional circuit board; a second PCIe connector located on the circuit board and coupled to the device, the second PCIe connector arranged to couple to a second connector of the additional circuit board a first additional connector located on the circuit board and coupled to the device, the first additional connector arranged to conduct signals based on a first computer network standard; and a second additional connector located on the circuit board and coupled to the device, the second additional connector arranged to conduct signals based on a second computer network standard. 10. The apparatus of claim 9 , wherein the circuit board includes a first edge, a second edge, and a third edge, the first PCIe connector includes conductors located at the first edge, and the second PCIe connector includes conductors located at the second edge, and the first and second additional connectors are located at the third edge. 11. An apparatus comprising: an integrated circuit (IC) chip; first conductive contacts of the IC chip arranged to couple to a first Peripheral Component Interconnect Express (PCIe) connector of a PCIe card; second conductive contacts of the IC chip arranged to couple to a second PCIe connector of the PCIe card; third conductive contacts arranged to couple to a first input/output (I/O) connector of the PCIe card; and fourth conductive contacts arranged to couple to a second I/O connector of the PCIe card, wherein the third conductive contacts are arranged to conduct signals from a first computer network through the first I/O connector of the PCIe card, and the fourth conductive contacts are arranged to conduct signals from a second computer network through the second I/O connector of the PCIe card. 12. The apparatus of claim 11 , wherein the first conductive contacts are arranged to conduct signals through a first point-to-point PCIe connection between the IC chip and one of components on a circuit board coupled to the IC chip through the first PCIe connector, and the second conductive contacts are arranged to conduct signals through a second point-to-point PCIe connection between the IC chip and one of the components on the circuit board coupled to the IC chip through the second PCIe connector. 13. The apparatus of claim 11 , wherein the first, second, third, and fourth conductive contacts include one of solder balls and conductive pins. 14. An electronic system comprising: a circuit board including a first Peripheral Component Interconnect Express (PCIe) slot and a second PCIe slot; and a PCIe card including a device, a first PCIe connector coupled to the device and the first PCIe slot, a second PCIe connector coupled to the device and the second PCIe slot, a first input/output (I/O) connector coupled to the device, and a second I/O connector coupled to the device, wherein each of the first and second PCIe connectors includes conductors, the conductors of first PCIe connector include a first group of conductors on a first side of the PCIe card, a second group of conductors on a second side of the PCIe card, the conductors of the second PCIe connector include a first group of conductors on the second side of the PCIe card, a second group of conductors on the first side of the PCIe card, the first group of conductors of each of the first and second PCIe connectors is arranged based on PCIe connector pin-out specification for a first side of a printed-circuit-board (PCB), and the second group of conductors of each of the first and second PCIe connectors is arranged based on PCIe connector pin-out specification for a second side of the PCB. 15. The electronic system of claim 14 , wherein the first PCIe connector is coupled to the first PCIe slot through a PCIe riser, and the second PCIe connector is coupled to the second PCIe slot through a PCIe extender cable. 16. The electronic system of claim 14 , wherein the PCIe card is arranged in parallel with the circuit board. 17. The electronic system of claim 14 , wherein the PCIe card is arranged perpendicular to the circuit boa

Assignees

Inventors

Classifications

  • cooperating directly with the edge of the rigid printed circuits · CPC title

  • on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

  • being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus · CPC title

  • Printed circuits being substantially perpendicular to each other (for printed connections H05K3/366) · CPC title

  • coupling devices mounted on the edge of the printed circuits · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US9710421B2 cover?
Some embodiments include apparatus and methods having a circuit board, a device located on the circuit board, a first Peripheral Component Interconnect Express (PCIe) connector located on the circuit board and coupled to the device, and a second PCIe connector located on the circuit board and coupled to the device. The first PCIe connector is arranged to couple to a first connector of an additi…
Who is the assignee on this patent?
Intel Corp
What technology area does this patent fall under?
Primary CPC classification G06F13/4282. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jul 18 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).