Techniques for adaptive interface support

Patent metadata

Field	Value
Publication number	US-9552316-B2
Application number	US-201414229870-A
Country	US
Kind code	B2
Filing date	Mar 29, 2014
Priority date	Mar 29, 2014
Publication date	Jan 24, 2017
Grant date	Jan 24, 2017

Abstract

Techniques for adaptive interface support are described. In one embodiment, for example, an apparatus may comprise logic, at least a portion of which is in hardware, the logic to execute a basic input/output system (BIOS), determine a respective impedance state for each of one or more pins in an M.2 physical interface, determine an interface type for a peripheral device coupled with the M.2 physical interface based on the impedance states for the one or more pins, and control an operational state of the peripheral device during execution of the BIOS, based on the interface type for the peripheral device. Other embodiments are described and claimed.

First claim

The invention claimed is:

1. An apparatus, comprising:
logic, at least a portion of which is in hardware, the logic to:
execute a basic input/output system (BIOS),
determine a respective impedance state for each of one or more pins in an M.2 physical interface, the one or more pins comprising one or more Peripheral Component Interconnect Express (PCIe) presence detect pins,
determine an interface type for a peripheral device coupled with the M.2 physical interface based on the impedance states for the one or more pins, and
control an operational state of the peripheral device during execution of the BIOS, based on the interface type for the peripheral device.

2. The apparatus of claim 1 , the peripheral device comprising a Wi-Fi adapter.

3. The apparatus of claim 1 , the logic to determine that the peripheral device comprises a PCIe device when it is determined that an electrical load is present on at least one of the one or more pins.

4. The apparatus of claim 3 , the logic to maintain the peripheral device in an active state and initialize the peripheral device using the BIOS when it is determined that the peripheral device comprises a PCIe device.

5. The apparatus of claim 1 , the logic to determine that the peripheral device comprises a Secure Digital Input/Output (SDIO) device when it is determined that each of the one or more pins is in a high-impedance state.

6. The apparatus of claim 5 , the logic to transition the peripheral device to a reset state, execute an operating system, and initialize the peripheral device using the operating system when it is determined that the peripheral device comprises an SDIO device.

7. The apparatus of claim 6 , the logic to transition the peripheral device to an active state after initializing the peripheral device using the operating system.

8. The apparatus of claim 1 , comprising:
a display;
a radio frequency (RF) transceiver; and
one or more RF antennas.

9. At least one non-transitory machine-readable medium comprising a set of instructions that, in response to being executed on a computing device, cause the computing device to:
execute a basic input/output system (BIOS) of the computing device;
determine a respective impedance state for each of one or more pins in an M.2 physical interface of the computing device, the one or more pins comprising one or more Peripheral Component Interconnect Express (PCIe) presence detect pins;
determine an interface type for a peripheral device coupled with the M.2 physical interface based on the impedance states for the one or more pins; and
control an operational state of the peripheral device during execution of the BIOS, based on the interface type for the peripheral device.

10. The at least one non-transitory machine-readable medium of claim 9 , the peripheral device comprising a Wi-Fi adapter.

11. The at least one non-transitory machine-readable medium of claim 9 , comprising instructions that, in response to being executed on the computing device, cause the computing device to determine that the peripheral device comprises a PCIe device when it is determined that an electrical load is present on at least one of the one or more pins.

12. The at least one non-transitory machine-readable medium of claim 11 , comprising instructions that, in response to being executed on the computing device, cause the computing device to maintain the peripheral device in an active state and initialize the peripheral device using the BIOS when it is determined that the peripheral device comprises a PCIe device.

13. The at least one non-transitory machine-readable medium of claim 9 , comprising instructions that, in response to being executed on the computing device, cause the computing device to determine that the peripheral device comprises a Secure Digital Input/Output (SDIO) device when it is determined that each of the one or more pins is in a high-impedance state.

14. The at least one non-transitory machine-readable medium of claim 13 , comprising instructions that, in response to being executed on the computing device, cause the computing device to transition the peripheral device to a reset state and initialize the peripheral device using an operating system of the computing device when it is determined that the peripheral device comprises an SDIO device.

15. The at least one non-transitory machine-readable medium of claim 14 , comprising instructions that, in response to being executed on the computing device, cause the computing device to transition the peripheral device to an active state after initializing the peripheral device using the operating system.

16. A method, comprising:
executing, by a processor circuit, a basic input/output system (BIOS) of a computing device;
determining a respective impedance state for each of one or more pins in an M.2 physical interface of the computing device, the one or more pins comprising one or more Peripheral Component Interconnect Express (PCIe) presence detect pins;
determining an interface type for a peripheral device coupled with the M.2 physical interface based on the impedance states for the one or more pins; and
controlling an operational state of the peripheral device during execution of the BIOS, based on the interface type for the peripheral device.

17. The method of claim 16 , the peripheral device comprising a Wi-Fi adapter.

18. The method of claim 16 , comprising determining that the peripheral device comprises a PCIe device when it is determined that an electrical load is present on at least one of the one or more pins.

19. The method of claim 18 , comprising maintaining the peripheral device in an active state and initializing the peripheral device using the BIOS when it is determined that the peripheral device comprises a PCIe device.

20. The method of claim 16 , comprising determining that the peripheral device comprises a Secure Digital Input/Output (SDIO) device when it is determined that each of the one or more pins is in a high-impedance state.

21. The method of claim 20 , comprising transitioning the peripheral device to a reset state and initializing the peripheral device using an operating system of the computing device when it is determined that the peripheral device comprises an SDIO device.

22. The method of claim 21 , comprising transitioning the peripheral device to an active state after initializing the peripheral device using the operating system.

Assignees

• Intel Corp

Inventors

• Desimone Nathaniel L
• Gough Robert E
• Dardis Sean C

Classifications

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F9/4411 Primary

  Configuring for operating with peripheral devices; Loading of device drivers · CPC title

• G06F9/4406

  Loading of operating system · CPC title

• G06F13/382 Primary

  using universal interface adapter · CPC title

• G06F13/4221

  being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus · CPC title