Bridge interconnection with layered interconnect structures

Patent metadata

Field	Value
Publication number	US-10475745-B2
Application number	US-201816129577-A
Country	US
Kind code	B2
Filing date	Sep 12, 2018
Priority date	May 28, 2013
Publication date	Nov 12, 2019
Grant date	Nov 12, 2019

Abstract

Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed.

First claim

What is claimed is:

1. An apparatus comprising:
a substrate having a cavity;
a bridge embedded in the substrate cavity;
a dielectric material laminated over the bridge in the cavity;
a joint electrically coupled with the bridge, to route electrical signals beyond a surface of the substrate, wherein the joint includes a first conductive material;
a barrier layer including a second conductive material disposed directly on the joint, and
a solder layer that includes a third conductive material, disposed directly on the barrier layer, wherein the barrier layer and the solder layer are to route the electrical signals.

2. The apparatus of claim 1 , wherein the joint comprises a via.

3. The apparatus of claim 1 , wherein the solder layer comprises a substantially round bump, formed by a reflow of the solder layer.

4. The apparatus of claim 1 , wherein the first conductive material comprises copper (Cu), the second conductive material comprises nickel (Ni), and the third conductive material comprises tin (Sn).

5. The apparatus of claim 1 , further comprising:
a first die electrically coupled with the bridge; and
a second die electrically coupled with the bridge.

6. The apparatus of claim 5 , wherein the first die includes a processor and the second die includes a memory die or another processor.

7. The apparatus of claim 1 , wherein the electrical signals are input/output (I/O) signals.

Assignees

• Intel Corp

Inventors

• Liu Yueli
• Zhang Qinglei
• Schuckman Amanda E
• Zhang Rui

Classifications

• H10W70/618

  the bridge chips being embedded in the package substrates, interposers or redistribution layers · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W72/07236

  Soldering or alloying · CPC title