Integrated circuit connection arrangement for minimizing crosstalk

Patent metadata

Field	Value
Publication number	US-10446687-B2
Application number	US-201916252168-A
Country	US
Kind code	B2
Filing date	Jan 18, 2019
Priority date	Feb 20, 2017
Publication date	Oct 15, 2019
Grant date	Oct 15, 2019

Abstract

A semiconductor package includes a leadframe, having perimeter package leads and a ground voltage lead, a bottom semiconductor die flip-chip mounted to the leadframe, and a top semiconductor die. The bottom semiconductor die has a first frontside active layer with first frontside electrical contacts electrically connected to the leadframe, a first backside portion, and a buried oxide layer situated between the first frontside active layer and the first backside portion. The top semiconductor die is mounted to the first backside portion. The first frontside active layer includes a circuit electrically connected to the first backside portion by a backside electrical connection through the buried oxide layer. The first backside portion of the bottom semiconductor die is electrically connected to the ground voltage lead through a first electrical contact of the first frontside electrical contacts to minimize crosstalk.

First claim

What is claimed is:

1. A method comprising:
providing a leadframe having perimeter package leads and a ground voltage lead;
forming a bottom semiconductor die comprising: i) a first frontside active layer having first frontside electrical contacts, ii) a first backside portion, and iii) a buried oxide layer, the buried oxide layer being situated between the first frontside active layer and the first backside portion;
flip-chip mounting the bottom semiconductor die to the leadframe, the flip-chip mounting comprising electrically connecting and physically mounting the first frontside electrical contacts of the bottom semiconductor die to the leadframe, a first electrical contact of the first frontside electrical contacts being electrically connected and physically mounted to the ground voltage lead of the leadframe;
providing a top semiconductor die, the top semiconductor die comprising: i) a second frontside having second frontside electrical contacts, and ii) a second backside; and
mounting the top semiconductor die to the bottom semiconductor die, the second backside of the top semiconductor die being attached to the first backside portion of the bottom semiconductor die;
wherein:
the first frontside active layer of the bottom semiconductor die comprises a circuit electrically connected to the first frontside electrical contacts by respective first frontside electrical connections and electrically connected to the first backside portion by a first backside connection through the buried oxide layer; and
the first backside portion of the bottom semiconductor die is electrically connected to the ground voltage lead of the leadframe through the first backside connection and the first electrical contact of the first frontside electrical contacts to minimize crosstalk.

2. The method of claim 1 , wherein:
an electrical contact of the second frontside electrical contacts of the top semiconductor die is electrically coupled to a first set of the perimeter package leads.

3. The method of claim 1 , wherein:
the bottom semiconductor die comprises two or more transistors;
at least one of the two or more transistors is electrically connected to the first frontside electrical contacts of the bottom semiconductor die; and
at least one of the two or more transistors is electrically connected to the first backside portion of the bottom semiconductor die.

4. The method of claim 3 , wherein:
the two or more transistors comprise a high-side transistor and a low-side transistor;
the high-side transistor comprises a high-side source, a high-side drain, and a high-side gate;
the low-side transistor comprises a low-side source, a low-side drain, and a low-side gate; and
the first backside portion of the bottom semiconductor die is electrically connected to the low-side source through the buried oxide layer.

5. The method of claim 4 , wherein:
a top electrical contact of the second frontside electrical contacts of the top semiconductor die is electrically connected to one or both of the high-side gate or the low-side gate.

6. The method of claim 5 , wherein:
the top electrical contact is electrically connected to the one or both of the high-side gate or the low-side gate through a perimeter package lead of the perimeter package leads of the leadframe.

7. The method of claim 4 , wherein:
the first electrical contact of the first frontside electrical contacts of the bottom semiconductor die is electrically connected to the low-side source.

8. The method of claim 7 , wherein:
a second electrical contact of the first frontside electrical contacts of the bottom semiconductor die electrically couples the low-side drain to the high-side source; and
the second electrical contact is electrically coupled and physically mounted to a phase node lead of the leadframe.

9. The method of claim 8 , wherein:
a third electrical contact of the first frontside electrical contacts of the bottom semiconductor die is electrically coupled to the high-side drain; and
the third electrical contact is electrically coupled and physically mounted to an input voltage node lead of the leadframe.

Assignees

• Silanna Asia Pte Ltd

Inventors

• Tu Shanghui Larry
• Stuber Michael A
• Tasbas Befruz
• Molin Stuart B
• Jiang Raymond

Classifications

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W72/871

  Bond wires and strap connectors · CPC title

• H10W72/926

  Multiple bond pads having different sizes · CPC title

• H10W90/766

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/761

  of strap connectors · CPC title