Method and apparatus for preventing inherent error propagation of successive approximation register analog-to-digital converter through digital correction

Patent metadata

Field	Value
Publication number	US-10425094-B2
Application number	US-201816001991-A
Country	US
Kind code	B2
Filing date	Jun 7, 2018
Priority date	Dec 1, 2017
Publication date	Sep 24, 2019
Grant date	Sep 24, 2019

Abstract

A method and apparatus for preventing inherent error propagation of a successive approximation register (SAR)-based analog-to-digital converter (ADC) through digital correction. A sample-and-hold circuit captures an input analog signal and generates a hold sample of the input analog signal. A digital-to-analog converter (DAC) generates an iterative sample corresponding to a digital code for each iteration. A comparator compares the hold sample and the iterative sample and generates a decision signal based on the comparison. A successive approximation register updates the digital code for each iteration based on the decision signal and supplies the updated digital code to the DAC. The SAR ADC includes an error detection circuit to detect an error condition. A controller ceases iteration operation if the error condition is detected and outputs the current digital code as a result.

First claim

What is claimed is:

1. A successive approximation register (SAR) analog-to-digital converter (ADC), comprising:
a sample-and-hold circuit configured to capture an input analog signal and generate a hold sample of the input analog signal;
a digital-to-analog converter (DAC) configured to generate an iterative sample corresponding to a digital code;
a comparator configured to compare the hold sample and the iterative sample and generate a decision signal based on the comparison;
a successive approximation register configured to update the digital code for each iteration based on the decision signal and supply an updated digital code to the DAC;
an error detection circuit configured to detect an error condition; and
a controller configured to cease iteration operation if the error condition is detected.

2. The SAR ADC of claim 1 , wherein the error condition is detected if the comparator outputs an indecisive value.

3. The SAR ADC of claim 1 , wherein the error condition is detected if an iteration register in the successive approximation register is updated with a value that is not expected from a previous iteration value.

4. The SAR ADC of claim 1 , wherein the successive approximation register includes:
an iteration register for storing a digital code;
a look-up table for generating a weight to be added to, and subtracted from, the digital code stored in the integration register to generate digital code candidates; and
a multiplexer for outputting one of the digital code candidates to the DAC based on the decision signal, wherein the output from the multiplexer is sent to the iteration register.

5. The SAR ADC of claim 4 , wherein the successive approximation register includes a latch for latching an output of the multiplexer.

6. The SAR ADC of claim 4 , wherein the error detection circuit includes:
candidate registers for storing the digital code candidates; and
logic equivalence circuits for determining whether a digital code output from the iteration register is same as one of the digital code candidates for each iteration,
wherein the controller ceases the iteration operation if the digital code output from the iteration register is not same as one of the digital code candidates.

7. The SAR ADC of claim 6 , wherein the error detection circuit includes a result candidate register for storing a digital code output from the iteration register, wherein a value stored in the result candidate register is output as a result if the error condition is detected.

8. A method for converting an analog signal to a digital signal, comprising:
capturing an input analog signal and generating a hold sample of the input analog signal;
generating, by a digital-to-analog converter (DAC), an iterative sample corresponding to a digital code;
comparing the hold sample and the iterative sample and generating a decision signal based on the comparison;
updating the digital code for each iteration based on the decision signal, wherein the iterative sample is generated from the updated digital code in each iteration;
detecting an error condition; and
ceasing iteration operation if the error condition is detected.

9. The method of claim 8 , wherein the error condition is detected if the comparator outputs an indecisive value.

10. The method of claim 8 , wherein the error condition is detected if an iteration register in the successive approximation register is updated with a value that is not expected from a previous iteration value.

11. The method of claim 8 , further comprising:
storing the digital code and the updated digital code in an iteration register;
generating a weight to be added to, and subtracted from, the digital code stored in the iteration register to generate digital code candidates; and
outputting one of the digital code candidates to the DAC based on the decision signal.

12. The method of claim 11 , wherein the one of the digital code candidates is latched temporarily before being sent to the DAC.

13. The method of claim 11 , wherein the error condition is detected if an updated digital code for a current iteration is not same as one of the digital code candidates.

14. The method of claim 11 , wherein a digital code output from the iteration register is stored in a temporary register, and output as a result if the error condition is detected.

Assignees

• Intel Corp

Inventors

• Traeber Mario

Classifications

• H03M1/462

  Details of the control circuitry, e.g. of the successive approximation register · CPC title

• H03M1/10

  Calibration or testing · CPC title

• H03M1/1071 Primary

  Measuring or testing · CPC title

• H03M1/0602

  of deviations from the desired transfer characteristic (H03M1/0617 takes precedence) · CPC title