Circuit and method for DAC mismatch error detection and correction in an ADC

Patent metadata

Field	Value
Publication number	US-9397679-B1
Application number	US-201615048597-A
Country	US
Kind code	B1
Filing date	Feb 19, 2016
Priority date	Feb 19, 2015
Publication date	Jul 19, 2016
Grant date	Jul 19, 2016

Abstract

A method comprises sampling an input voltage signal, comparing the sampled input voltage signal with an output signal of a feedback DAC, and determining an (N+1) bit code representation for a comparison result, the (N+1) bit code yielding the N bit output signal. On detection of the (N+1) bit code being equal to a predefined calibration trigger code, performing a calibration for a most significant bit of the (N+1) bit code by replacing the (N+1) bit code by an alternative (N+1) bit code that yields the same N bit output signal, performing an additional comparison cycle using the alternative (N+1) bit code, determining, using comparison results of the additional comparison cycle and the preceding (N+1) th cycle, a sign of a DAC capacitor mismatch error, and tuning programmable binary scaled calibration capacitors in parallel to a capacitor corresponding to the one of the most significant bits of the (N+1) bit code.

First claim

What is claimed is:

1. A method for calibrating an analog-to-digital converter (ADC) converting an input voltage signal into a N bit output signal representing the input voltage signal, the method comprising:
sampling the input voltage signal applied to the ADC;
comparing the sampled input voltage signal with an output signal of a feedback digital-to-analogue converter (DAC);
determining, in a search logic block of the ADC, a (N+1) bit code representation for a result of the comparison, the (N+1) bit code yielding the N bit output signal; and
responsive to detection of the (N+1) bit code being equal to a predefined calibration trigger code, performing a calibration for one of the most significant bits of the (N+1) bit code by:
replacing the (N+1) bit code by an alternative (N+1) bit code that yields the same N bit output signal;
performing an additional comparison cycle using the alternative (N+1) bit code;
determining, using the comparison results of the additional comparison cycle and of the preceding (N+ 1 ) th cycle, a sign of a DAC capacitor mismatch error;
tuning, in accordance with the sign of the DAC capacitor mismatch error, a set of switchable binary scaled calibration capacitors in parallel to a capacitor of the DAC, the capacitor corresponding to the one bit of the most significant bits of the (N+1) bit code for which the calibration is performed.

2. The method for calibrating as in claim 1 , wherein the sign of the DAC capacitor mismatch error is stored in a calibration register.

3. The method for calibrating as in claim 1 , further comprising applying a low pass filtering to a signal comprising the sign of the DAC capacitor mismatch error.

4. An analogue-to-digital converter for converting an input voltage signal into an N-bit output signal representing the input voltage signal, the analogue-to-digital converter comprising:
sampling means for sampling the input voltage signal;
comparator arranged for receiving the sampled input voltage signal;
a digital-to-analogue converter (DAC) comprising an array of capacitors;
a search logic block arranged for receiving a comparator output signal from the comparator, for providing an input to the DAC, and for producing an (N+1) bit code representation for the comparator results, the (N+1) bit code yielding the N bit output signal;
a calibration block arranged for performing a calibration algorithm comprising:
replacing the (N+1) bit code by an alternative (N+1) bit code that yields the same N bit output signal;
performing an additional comparison cycle using the alternative (N+1) bit code;
determining a sign of a DAC capacitor mismatch error; and
using comparison results of the additional comparison cycle and a preceding (N+1) th cycle and tuning, in accordance with the sign of the DAC capacitor mismatch error, a set of switchable binary scaled calibration capacitors in parallel to a capacitor of the DAC, the capacitor corresponding to the one bit of the most significant bits of the (N+1) bit code for which the calibration is performed; and

detection means for detecting whether the (N+1) bit code is equal to a predefined calibration trigger code, and for activating the calibration block.

5. The analogue-to-digital converter as in claim 4 , wherein search logic block is implemented as a successive approximation register.

Assignees

• Stichting Imec Nederland

Inventors

• Harpe Pieter

Classifications

• H03M1/466

  using switched capacitors · CPC title

• H03M1/1014 Primary

  at one point of the transfer characteristic, i.e. by adjusting a single reference value, e.g. bias or gain error (gain setting for range control H03M1/18) · CPC title

• H03M1/069

  by range overlap between successive stages or steps · CPC title

• H03M1/1071

  Measuring or testing · CPC title

• H03M1/38

  sequentially only, e.g. successive approximation type (converting more than one bit per step H03M1/14) · CPC title