Method of gain calibration in a successive approximation register analog-to-digital converter and a successive approximation register analog-to-digital converter

Patent metadata

Field	Value
Publication number	US-10050638-B2
Application number	US-201715835310-A
Country	US
Kind code	B2
Filing date	Dec 7, 2017
Priority date	Dec 8, 2016
Publication date	Aug 14, 2018
Grant date	Aug 14, 2018

Abstract

A method of gain calibration in a SAR ADC is disclosed. In one aspect, the method comprises determining a number of bits of an analog input signal (VIN), detecting if a binary code determined from the analog input signal (VIN) matches at least one trigger code, using at least one setting code to determine a calibration residue signal (V*RES) and a calibration bit (B*LSB), analyzing a least significant bit of the digital signal (COUT) and the calibration bit (B*LSB), determining an indication of a presence of gain error in the gain module, and calibrating the gain error. As the determination of the calibration bit (B*LSB) requires only one additional comparison, as compared to normal operation, the normal operation does not need to be interrupted. Therefore, the calibration can be done in the background and, as such, can be performed frequently thereby taking into account time-varying changes due to environmental effects.

First claim

What is claimed is:

1. A method of gain calibration in a successive approximation register analog-to-digital converter, SAR ADC, the method comprising:
determining, by a first stage ADC, a number of most significant bits (B MSB ) of a digital signal (C OUT ) corresponding to an analog input signal (V IN );
amplifying, by a gain module, a residue signal (V RES ) output from the first stage ADC; and
determining, by a second stage ADC, a number of least significant bits (B LSB ) of the digital signal (C OUT ) corresponding to the analog input signal (V IN );
detecting if a binary code determined from the analog input signal (V IN ) matches at least one trigger code;
using at least one setting code corresponding to the at least one trigger code to determine a calibration residue signal (V* RES ) in the first stage ADC and a calibration bit (B* LSB ) in the second stage ADC;
analyzing a least significant bit of the digital signal (C OUT ) and the calibration bit (B* LSB );
determining, from the analysis, an indication of a presence of gain error in the gain module; and
calibrating gain error in the gain module if the presence of gain error is determined.

2. The method according to claim 1 , wherein the step of using at least one setting code further comprises determining the calibration residue signal (V* RES ) by calculating a difference between the analog input signal (V IN ) and an analog signal (V* MSB ) representing a part of the at least one setting code.

3. The method according to claim 1 , wherein the step of using at least one setting code further comprises determining the calibration bit (B* LSB ) by comparing an amplified calibration residue signal (V* AMP ) to a further analog signal (V* LSB ) representing a part of the at least one setting code.

4. The method according to claim 1 , wherein the step of using at least one setting code further comprises temporarily storing, by the gain module, the calibration residue signal (V* RES ) until the least significant bit has been determined.

5. The method according to claim 1 , wherein the step of determining an indication of a presence of gain error further comprises determining if the least significant bit and the calibration bit (B* LSB ) are different indicating the presence of gain error in the gain module.

6. The method according to claim 5 , wherein the step of determining an indication of a presence of gain error further comprises determining the value of the least significant bit, and, if it has a value of 1, indicating a downwards calibration, and, if it has a value of 0, indicating an upwards calibration.

7. The method according to claim 1 , wherein the step of determining an indication of a presence of gain error further comprises determining the value of the least significant bit and of the calibration bit (B* LSB ), and, if the value of both the least significant bit and the calibration bit (B* LSB ) is 0, not indicating the presence of gain error in the gain module, and, if the value of both the least significant bit and the calibration bit (B* LSB ) is 1, not indicating the presence of gain error in the gain module, and if the value of the least significant bit is 0 and the value of the calibration bit (B* LSB ) is 1, indicating the presence of gain error in the gain module with an upwards calibration, and if the value of the least significant bit is 1 and the value of the calibration bit (B* LSB ) is 0, indicating the presence of gain error in the gain module with a downwards calibration.

8. The method according to claim 1 , wherein the step of calibrating gain error in the gain module further comprises, upon detecting presence of gain error in the gain module, calibrating the second stage ADC by adjusting at least one of a plurality of tunable capacitors.

9. A successive approximation register analog-to-digital converter, SAR ADC, comprising:
a first stage ADC configured for determining a number of most significant bits (B MSB ) of a digital signal (C OUT ) corresponding to an analog input signal (V IN ) and for outputting a residue signal (V RES ) corresponding to a number of least significant bits (B LSB ) of the digital signal (C OUT );
a gain module configured for receiving the residue signal (V RES ) output from the first stage ADC, for amplifying the residue signal (V RES ) and for outputting the amplified residue signal (V AMP );
a second stage ADC configured for receiving the amplified residue signal (V AMP ) and for determining a number of least significant bits (B LSB ) of the digital signal (C OUT ) corresponding to the input analog signal (V IN ) from the amplified residue signal (V AMP ); and
a control module configured for controlling the first stage ADC, the gain module, and the second stage ADC, and for outputting the digital output signal (C OUT ) corresponding to the input analog signal (V IN );
wherein the control module is further configured for:
storing at least one trigger code;
detecting if a binary code determined from the analog input signal (V IN ) matches the at least one trigger code;
providing at least one setting code corresponding to the at least one trigger code to the first stage ADC that is further configured for determining a calibration residue signal (V* RES ), and, to the second stage ADC that is further configured for determining a calibration bit (B* LSB );
analyzing a least significant bit of the digital signal (C OUT ) and the calibration bit (B* LSB );
determining, from the analysis, an indication of a presence of gain error in the gain module; and
initiating calibrating gain error in the gain module if the presence of gain error is determined.

10. The SAR ADC according to claim 9 , wherein the first stage ADC comprises a residue generation module that is configured for determining the calibration residue signal (V* RES ) by calculating a difference between the analog input signal (V IN ) and an analog signal (V* MSB ) representing a part of the at least one setting code.

11. The SAR ADC according to claim 9 , wherein the second stage ADC comprises a comparator configured for determining the calibration bit (B* LSB ) by comparing an amplified calibration residue signal (V* AMP ) to a further analog signal (V* LSB ) representing a part of the at least one setting code.

12. The SAR ADC according to claim 9 , wherein the gain module comprises: a first amplifier, a second amplifier, a first switch between the first amplifier and the second amplifier, and a second switch after the second amplifier, the control module controlling the first switch and the second switch to store temporarily the calibration residue signal (V* RES ) on a capacitor (C S ) after the first switch until the second stage ADC has determined the least significant bit.

13. The SAR ADC according to claim 9 , wherein the control module further comprises a difference calculation module configured for determining if the least significant bit and the calibration bit (B* LSB ) are different indicating the presence of gain error in the gain module.

14. The SAR ADC according to claim 13 , wherein the control module comprises a gain calibration module configured for determining the value of the least significant bit, and, if it has a value of 1, indicating a downwards calibration, and, if it has a value of 0, indicating an upwards calibration.

15. The SAR ADC according to claim 9 , wherein the control module is further configured to send a signal indicating the presence of gain error in the gain module to the second stage ADC that comprises a plurality of tunable capacitors configured to be adjusted in accordance with the signal.

Assignees

• Stichting Imec Nederland

Inventors

• Ding Ming
• Harpe Pieter
• Li Hanyue

Classifications

• H03M1/1009 Primary

  Calibration · CPC title

• H03M1/1014 Primary

  at one point of the transfer characteristic, i.e. by adjusting a single reference value, e.g. bias or gain error (gain setting for range control H03M1/18) · CPC title

• H03M1/44

  Sequential comparisons in series-connected stages with change in value of analogue signal · CPC title

• H03M1/46

  with digital/analogue converter for supplying reference values to converter · CPC title