Method of digital-to-analog converter mismatch calibration in a successive approximation register analog-to-digital converter and a successive approximation register analog-to-digital converter

Patent metadata

Field	Value
Publication number	US-10027339-B2
Application number	US-201715833796-A
Country	US
Kind code	B2
Filing date	Dec 6, 2017
Priority date	Dec 8, 2016
Publication date	Jul 17, 2018
Grant date	Jul 17, 2018

Abstract

A method of DAC mismatch calibration in a SAR ADC is disclosed. In one aspect, the method comprises determining a number of bits of an analog input signal (V IN ), detecting if a binary code determined from the analog input signal (V IN ) matches at least one trigger code, using at least one setting code to determine a calibration residue signal (V* RES ) and a calibration bit (B* LSB ), analyzing a least significant bit of the digital signal (C OUT ) and the calibration bit (B* LSB ), determining an indication of a presence of DAC mismatch, and calibrating the DAC mismatch. As the determination of the calibration bit (B* LSB ) requires only one additional comparison, when compared to the normal operation, the normal operation does not need to be interrupted. Therefore, the calibration can be done in the background and, as such, can be performed frequently thereby taking into account time-varying changes due to environmental effects.

First claim

What is claimed is:

1. A method of digital-to-analog converter (DAC) mismatch calibration in a successive approximation register (SAR) analog-to-digital converter (ADC), the method comprising the steps of:
determining, by a first stage ADC, a number of most significant bits (B MSB ) of a digital signal (C OUT ) corresponding to an analog input signal (V IN );
amplifying, by a gain module, a residue signal (V RES ) output from the first stage ADC;
determining, by a second stage ADC, a number of least significant bits (BLSB) of the digital signal (C OUT ) corresponding to the analog input signal (V IN );
detecting if a binary code determined from the analog input signal (V IN ) matches at least one trigger code;
using at least one setting code corresponding to the at least one trigger code to determine a calibration residue signal (V* RES ) in the first stage ADC and a calibration bit (B* LSB ) in the second stage ADC;
analyzing a least significant bit of the digital signal (C OUT ) and the calibration bit (B* LSB );
determining, from the analysis, an indication of a presence of DAC mismatch between a first DAC in the first stage ADC and a second DAC in the second stage ADC; and
calibrating DAC mismatch between the first DAC and the second DAC if the presence of DAC mismatch is determined.

2. The method of claim 1 , wherein determining the calibration residue signal (V* RES ) further comprises calculating a difference between the analog input signal (V IN ) and an analog signal (V* MSB ) representing a part of the at least one setting code.

3. The method of claim 1 , wherein determining the calibration bit (B* LSB ) further comprises comparing an amplified calibration residue signal (V* AMP ) to a further analog signal (V* LSB ) representing a part of the at least one setting code.

4. The method of claim 1 , further comprising temporarily storing, by the gain module, the calibration residue signal (V* RES ) until the least significant bit of the digital signal (C OUT ) has been determined.

5. The method of claim 1 , wherein determining an indication of DAC mismatch further comprises determining if the least significant bit and the calibration bit (B* LSB ) are different.

6. The method of claim 5 , wherein determining an indication of DAC mismatch further comprises determining the value of the least significant bit, and, if it has a value of 0, indicating a downwards calibration, and, if it has a value of 1, indicating an upwards calibration.

7. The method of claim 1 , wherein determining an indication of DAC mismatch further comprises determining the value of the least significant bit and of the calibration bit (B* LSB ), and, if the value of both bits is 0, not indicating the presence of DAC mismatch between the first DAC and the second DAC, and, if the value of both bits is 1, not indicating the presence of DAC mismatch between the first DAC and the second DAC, and if the value of the least significant bit is 1 and the value of the calibration bit (B* LSB ) is 0, indicating the presence of DAC mismatch between the first DAC and the second DAC with an upwards calibration, and if the value of the least significant bit is 0 and the value of the calibration bit (B* LSB ) is 1, indicating the presence of DAC mismatch between the first DAC and the second DAC with a downwards calibration.

8. The method of claim 1 , wherein calibrating DAC mismatch further comprises calibrating the first stage ADC by adjusting at least one of a plurality of tunable capacitors.

9. A successive approximation register (SAR) analog-to-digital converter (ADC) comprising:
a first stage ADC configured to determine a number of most significant bits (B MSB ) of a digital signal (C OUT ) corresponding to an analog input signal (V IN ) and further configured to output a residue signal (V RES ) corresponding to a number of least significant bits (B LSB ) of the digital signal (C OUT );
a gain module configured to receive the residue signal (V RES ) output from the first stage ADC, further configured to amplify the residue signal (V RES ), and further configured to output the amplified residue signal (V AMP );
a second stage ADC configured to receive the amplified residue signal (V AMP ) and further configured to determine a number of least significant bits (B LSB ) of the digital signal (C OUT ) corresponding to the input analog signal (V IN ) from the amplified residue signal (V AMP ); and
a control module configured to:
control the first stage ADC, the gain module, and the second stage ADC;
output the digital output signal (C OUT ) corresponding to the input analog signal (V IN );
store at least one trigger code;
detect if a binary code determined from the analog input signal (V IN ) matches the at least one trigger code;
provide at least one setting code corresponding to the at least one trigger code to the first stage ADC, wherein the first stage ADC is further configured to determine a calibration residue signal (V* RES );
provide at least one setting code corresponding to the at least one trigger code to the second stage ADC, wherein the second stage ADC is further configured to determine a calibration bit (B* LSB );
analyze a least significant bit of the digital signal (C OUT ) and the calibration bit (B* LSB );
determine, from the analysis, an indication of a presence of DAC mismatch between a first DAC in the first stage ADC and a second DAC in the second stage ADC; and
initiate DAC mismatch calibration between the first DAC and the second DAC if the presence of DAC mismatch is determined.

10. The SAR ADC of claim 9 , wherein the first stage ADC comprises a residue generation module configured to determine the calibration residue signal (V* RES ) by calculating a difference between the analog input signal (V IN ) and an analog signal (V* MSB ) representing a part of the at least one setting code.

11. The SAR ADC of claim 9 , wherein the second stage ADC comprises a comparator configured to determine the calibration bit (B* LSB ) by comparing an amplified calibration residue signal (V* AMP ) to a further analog signal (V* LSB ) representing a part of the at least one setting code.

12. The SAR ADC of claim 9 , wherein the gain module comprises: a first amplifier, a second amplifier, a first switch between the first amplifier and the second amplifier, and a second switch after the second amplifier, the control module controlling the first switch and the second switch to store temporarily the calibration residue signal (V* RES ) until the second stage ADC has determined the least significant bit.

13. The SAR ADC of claim 9 , wherein the control module further comprises a difference calculation module configured to determine if the least significant bit and the calibration bit (B* LSB ) are different indicating the presence of DAC mismatch between the first DAC and the second DAC.

14. The SAR ADC of claim 13 , wherein the control module comprises a DAC mismatch calibration module configured to determine the value of the least significant bit, and, if it has a value of 0, indicating a downwards calibration, and, if it has a value of 1, indicating an upwards calibration.

15. The SAR ADC of claim 9 , wherein the control module is further configured to send a signal indicating the presence of DAC mismatch between the first DAC and the second DAC to the first stage ADC that comprises a plurality of tunable capacitors configured to be adjusted in accordance with the signal.

Assignees

• Stichting Imec Nederland

Inventors

• Ding Ming
• Harpe Pieter
• Li Hanyue

Classifications

• H03M1/462

  Details of the control circuitry, e.g. of the successive approximation register · CPC title

• H03M1/1023 Primary

  Offset correction (H03M1/1019 takes precedence; removal of offset already present on the analogue input signal H03M1/1295) · CPC title

• H03M1/1047

  using an auxiliary digital/analogue converter for adding the correction values to the analogue signal (H03M1/1052 takes precedence) · CPC title

• H03M1/108

  Converters having special provisions for facilitating access for testing purposes · CPC title

• H03M1/0675

  using redundancy · CPC title