Successive approximation register analog-to-digital converter applying calibration circuit, associated calibrating method, and associated electronic device

Patent metadata

Field	Value
Publication number	US-10128862-B2
Application number	US-201715401106-A
Country	US
Kind code	B2
Filing date	Jan 9, 2017
Priority date	Jan 21, 2016
Publication date	Nov 13, 2018
Grant date	Nov 13, 2018

Abstract

A Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) including: a comparing module and a calibration circuit. The comparing module is arranged to generate a first comparison result by comparing an input voltage value of the SAR ADC with a first voltage value and a second result by comparing the input voltage value with a second voltage value; the calibration circuit coupled to the comparing module is for generating a determination result determining whether the input voltage value is in a range according to the first comparison result and the second comparison result, and enters a calibration mode according to the determination result.

First claim

What is claimed is:

1. A successive approximation register (SAR) analog-to-digital converter (ADC) comprising:
a comparing module, arranged to generate a first comparison result by comparing an input voltage value of the SAR ADC with a first voltage value and a second result by comparing the input voltage value with a second voltage value;
a calibration circuit, coupled to the comparing module, for generating a determination result determining whether the input voltage value is in a range according to the first comparison result and the second comparison result, and enters a calibration mode according to the determination result;
wherein when the determination result indicates that the input voltage value is between the first voltage value and the second voltage value, the calibration circuit enters the calibration mode to perform a weighted number calibration; and when the determination result indicates that the input voltage value is not between the first voltage value and the second voltage value, the calibration circuit stays in a normal mode and not perform a weighted number calibration.

2. The SAR ADC of claim 1 , comprising:
a SAR logic circuit, arranged to generate an n-bit output signal, wherein n is a positive integer;
wherein the calibration circuit performs the weighted number calibration for at least one bit of the n-bit output signal of the SAR logic circuit according to the determination result.

3. The SAR ADC of claim 2 , wherein each of the at least one bit of the n-bit output signal corresponds to a weighted number.

4. The SAR ADC of claim 3 , wherein the calibration circuit sequentially and repeatedly performing the weighted number calibration for each of the at least one bit of the n-bit output signal, the n th bit is a most significant bit of the output signal.

5. The SAR ADC of claim 3 , wherein the calibration circuit performs the weighted number calibration to generate at least one calibrating value, and the SAR ADC further comprises:
a digital correction circuit, coupled to the calibration circuit, configured to adjust the weighted number by using the calibrating value to generate an adjusted weighted number, and generate a digital output according to the adjusted weighted number and the n-bit output signal of the SAR logic circuit.

6. The SAR ADC of claim 2 , wherein the calibration circuit adjusts the weighted number corresponding to the bit comprises:
setting the bit of the output signal of the SAR logic circuit to be a first logic value in order to generate a first output result;
setting the bit of the output signal of the SAR logic circuit to be a second logic value different from the first logic value in order to generate a second output result, wherein each of the first output result and the second output result is generated from a weighted summation of the output signal of the SAR logic circuit after setting the bit to be one of the first logic value and the second logic value; and
adjusting a weighted number corresponding to the bit of the output signal according to the first output result and the second output result;
wherein when the bit of the output signal of the SAR logic circuit is set by the first logic value or the second logic value, a common voltage is provided to a plurality of capacitors of the SAR ADC corresponding to a bit next to the bit on a left hand side to the n th bit of the output signal of the SAR logic circuit.

7. The SAR ADC of claim 2 , further comprising:
a capacitor-based digital-to-analog converter (DAC), comprising:
a plurality of capacitors, wherein each capacitor corresponds to each of the at least one bit; and
a plurality of switches, corresponding to the plurality of capacitor.

8. A calibrating method of a successive approximation register (SAR) analog-to-digital converter (ADC), comprising:
generating a first comparison result by comparing an input voltage value of the SAR ADC with a first voltage value and generating a second comparison result by comparing the input voltage value with a second voltage value;
determining whether the SAR ADC enters into a calibration mode with reference to whether the input voltage value of the SAR ADC is between the first voltage value and the second voltage value;
generating an n-bit output signal, wherein n is a positive integer;
when it is determined that the input voltage value is between the first voltage value and the second voltage value, performing a weighted number calibration for each of at least one bit of the n-bit output signal when the input voltage value of the SAR ADC is in the predetermined range, wherein each of the at least one bit of the n-bit output signal corresponds to a weighted number; and
when it is determined that the input voltage value is not between the first voltage value and the second voltage value, not performing the weighted number calibration;
wherein the weighted number calibration for each of the at least one bit of the n-bit output signal comprises:
adjusting a weighted number corresponding to the bit.

9. The calibrating method of claim 8 , wherein the SAR ADC is an n-bit SAR ADC and comprises a SAR logic circuit outputting the n-bit output signal, and n th bit is a most significant bit of the output signal, further comprising:
sequentially and repeatedly performing the weighted number calibration for each of the at least one bit of the n-bit output signal of the SAR logic circuit.

10. The calibrating method of claim 9 , wherein the step of adjusting the weighted number corresponding to the bit comprises:
setting the bit of the output signal of the SAR logic circuit to be a first logic value to generate a first output result;
setting the bit of the output signal of the SAR logic circuit to be a second logic value different from the first logic value to generate a second output result, wherein each of the first output result and the second output result is generated from a weighted summation of the output signal of the SAR logic circuit after setting the bit to be one of the first logic value and the second logic value; and
adjusting a weighted number corresponding to the bit of the output signal according to the first output result and the second output result;
wherein when the bit of the output signal of the SAR logic circuit is set by the first logic value or the second logic value, a common voltage is provided to a plurality of capacitors of the SAR ADC corresponding to a bit next to the bit on a left hand side to the n th bit of the output signal of the SAR logic circuit.

11. The calibrating method of claim 10 , wherein the first output result is generated by setting the bit of the output signal of the SAR logic circuit to be the first logic value in order to sum the weighted summation of the output signal of the SAR logic circuit for a predetermined number of times; and the second output result is generated by setting the bit of the output signal of the SAR logic circuit to be the second logic value in order to sum the weighted summation of the output signal of the SAR logic circuit for a predetermined number of times.

12. The calibrating method of claim 10 , wherein the first logic value is logic value 0, and the second logic value is logic value 1; and adjusting the weighted number corresponding to the bit further comprises:
when the first output result is greater than the second output result, adding a predetermined calibrating value to the weighted number corresponding to the bit of the output signal of the SAR logic circuit.

13. The calibrating method of claim 12 , wherein the predetermined calibrating value is a quarter of a value corresponding to a least significant bit of

Assignees

• Mediatek Inc

Inventors

• Liu Chun-Cheng

Classifications

• H03M1/1009 Primary

  Calibration · CPC title

• H03M1/1042 Primary

  the look-up table containing corrected values for replacing the original digital values (H03M1/1052 takes precedence) · CPC title

• H03M1/0692

  using a diminished radix representation, e.g. radix 1.95 · CPC title

• H03M1/001

  Analogue/digital/analogue conversion · CPC title

• H03M1/468

  in which the input S/H circuit is merged with the feedback DAC array · CPC title