Semiconductor device

Patent metadata

Field	Value
Publication number	US-10424513-B2
Application number	US-201816005886-A
Country	US
Kind code	B2
Filing date	Jun 12, 2018
Priority date	Nov 22, 2017
Publication date	Sep 24, 2019
Grant date	Sep 24, 2019

Abstract

A semiconductor device, comprising: a substrate which includes an active circuit region, and a boundary region surrounding the active circuit region, the boundary region including an edge portion of the substrate; a first lower conductive pattern disposed on the substrate of the boundary region; and a first upper conductive pattern connected to the first lower conductive pattern over the first lower conductive pattern, wherein the first upper conductive pattern includes a first portion having a first thickness, a second portion having a second thickness greater than the first thickness, and a third portion having a third thickness greater than the second thickness, and the third portion of the first upper conductive pattern is connected to the first lower conductive pattern, is provided.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate including an active circuit region and a boundary region surrounding the active circuit region, the boundary region including an edge portion of the substrate;
a first lower conductive pattern on the substrate of the boundary region;
a first upper conductive pattern connected to the first lower conductive pattern over the first lower conductive pattern; and
a second upper conductive pattern spaced apart from the first upper conductive pattern at the same metal level of the first upper conductive pattern, on the substrate of the boundary region,
wherein the first upper conductive pattern includes a first portion having a first thickness, a second portion having a second thickness greater than the first thickness, and a third portion having a third thickness greater than the second thickness,
the third portion of the first upper conductive pattern is connected to the first lower conductive pattern, and
the second upper conductive pattern includes a fourth portion having a fourth thickness substantially the same as the second thickness and a fifth portion having a fifth thickness substantially the same as the third thickness.

2. The semiconductor device of claim 1 , wherein the first portion of the first upper conductive pattern is between the second portion of the first upper conductive pattern and the third portion of the first upper conductive pattern.

3. The semiconductor device of claim 1 , wherein the first upper conductive pattern further includes a sixth portion having a sixth thickness which is greater than the first thickness and smaller than the third thickness.

4. The semiconductor device of claim 3 , wherein the second thickness is substantially the same as the sixth thickness.

5. The semiconductor device of claim 1 , wherein the first lower conductive pattern includes a seventh portion having a seventh thickness, and an eighth portion having an eighth thickness greater than the seventh thickness, and
the eighth portion of the first lower conductive pattern is connected to a conductive material below the first lower conductive pattern.

6. The semiconductor device of claim 5 , wherein the first lower conductive pattern includes a ninth portion which has a ninth thickness which is greater than the seventh thickness and smaller than the eighth thickness, and
the seventh portion of the first lower conductive pattern is between the eighth portion of the first lower conductive pattern and the ninth portion of the first lower conductive pattern.

7. The semiconductor device of claim 1 , further comprising:
a fin type pattern, and a gate electrode on the fin type pattern, in the active circuit region,
wherein a height from the substrate to an upper surface of the gate electrode is smaller than a height from the substrate to the first lower conductive pattern.

8. The semiconductor device of claim 1 , wherein the third portion of the first upper conductive pattern is in contact with the first lower conductive pattern.

9. A semiconductor device comprising:
a substrate including an active circuit region and a boundary region surrounding the active circuit region;
a first fin type pattern on the substrate of the active circuit region;
a gate electrode on the first fin type pattern;
a pre-metal insulating layer on the first fin type pattern and the gate electrode;
a first lower conductive pattern and a second lower conductive pattern at a first metal level on the pre-metal insulating layer and apart from each other, in the boundary region;
a first upper conductive pattern at a second metal level higher than the first metal level and connected to the first lower conductive pattern; and
a second upper conductive pattern at the second metal level, apart from the first upper conductive pattern, and connected to the second lower conductive pattern,
wherein the first upper conductive pattern includes a first portion having a first thickness, a second portion having a second thickness greater than the first thickness, and a third portion having a third thickness greater than the second thickness,
the first portion of the first upper conductive pattern is between the second portion of the first upper conductive pattern and the third portion of the first upper conductive pattern, and
the second upper conductive pattern includes a fourth portion having a fourth thickness substantially the same as the second thickness and a fifth portion having a fifth thickness substantially the same as the third thickness.

10. The semiconductor device of claim 9 , wherein the third portion of the first upper conductive pattern is in contact with the first lower conductive pattern.

11. The semiconductor device of claim 9 , wherein
the fifth portion of the second upper conductive pattern is in contact with the second lower conductive pattern.

12. The semiconductor device of claim 9 , further comprising:
a pair of second fin type patterns on the substrate of the boundary region; and
a conductive plug between the second fin type patterns and connected to the first lower conductive pattern.

13. The semiconductor device of claim 9 , further comprising:
a wiring structure on the pre-metal insulating layer and connected to the gate electrode, in the active circuit region,
wherein the wiring structure is at the first metal level and the second metal level.

14. A semiconductor device comprising:
a substrate including an active circuit region, and a boundary region surrounding the active circuit region, the boundary region including an edge portion of the substrate; and
a first conductive guard structure and a second conductive guard structure spaced apart from the first conductive guard structure surrounding the active circuit region on the substrate of the boundary region,
wherein the first conductive guard structure includes a first plate pattern, a second plate pattern on the first plate pattern, and a via pattern for connecting the first plate pattern and the second plate pattern,
the second plate pattern is apart from the first plate pattern,
the second plate pattern includes a first portion having a first thickness, and a second portion having a second thickness greater than the first thickness,
the second conductive guard structure includes a third plate pattern at the same metal level as the second plate pattern, and
the third plate pattern includes a third portion having a third thickness substantially the same as the second thickness.

15. The semiconductor device of claim 14 ,
wherein the second conductive guard structure is closer to the active circuit region than the first conductive guard structure.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Jung Il
• Ahn Jeong Hoon
• Lee Joon-Nyung

Classifications

• H10W42/121

  protecting against mechanical damage (H10W76/00, H10W74/00 take precedence) · CPC title

• H10W42/00

  Arrangements for protection of devices (arrangements for thermal protection H10W40/00) · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/087

  involving multiple stacked pre-patterned masks · CPC title