Stitch and trim methods for double patterning compliant standard cell design

Patent metadata

Field	Value
Publication number	US-9384307-B2
Application number	US-201313970636-A
Country	US
Kind code	B2
Filing date	Aug 20, 2013
Priority date	Dec 30, 2011
Publication date	Jul 5, 2016
Grant date	Jul 5, 2016

Abstract

A method for creating double patterning compliant integrated circuit layouts is disclosed. The method allows patterns to be assigned to different masks and stitched together during lithography. The method also allows portions of the pattern to be removed after the process.

First claim

What is claimed is:

1. A method, comprising:
providing a non-transitory machine readable storage medium encoded with data representing a cell layout having patterns including a bus pattern, wherein the patterns of the cell layout are assigned into respective sets to be patterned using at least a first mask and a second mask for patterning a single layer of an IC;
assigning a first portion of the bus pattern to be patterned by the first mask and a second portion of the bus pattern to be patterned by the second mask;
assigning an overlap portion of the bus pattern to be patterned using the first mask and the second mask, including:
assigning a rectangular portion within the bus pattern to the second mask, and
assigning a polygon within the bus pattern and surrounding the rectangle on three sides to the first mask, wherein three respective sides of the rectangle overlap with respective overlap portions of the polygon; and

outputting the cell layout to a machine readable storage medium to be read by a system for controlling a process to fabricate the first and second masks for patterning a semiconductor substrate using the first and second masks to pattern a single layer.

2. The method of claim 1 , wherein the overlap portion of the bus pattern assigned to the second mask extends partially across the width of the bus pattern in a direction parallel to the shorter dimension of the bus.

3. The method of claim 2 , wherein the overlap portion of the bus pattern assigned to the second mask abuts a second portion of the bus pattern assigned to the first mask outside of the overlap portion of the first mask.

4. The method of claim 1 , wherein the cell layout has an interior region containing a circuit pattern, and the overlap portion of the first mask is positioned on a longitudinal edge of the bus pattern distal from the circuit pattern.

5. The method of claim 4 , wherein the circuit pattern is positioned at a given distance from a nearest corner of the overlap region, the given distance being smaller than a spacing rule for a distance between patterns.

6. The method of claim 4 , wherein the circuit pattern is assigned to the first mask.

7. The method of claim 1 , wherein:
the overlap portion of the bus pattern assigned to the second mask extends partially across the width of the bus pattern in a direction parallel to the shorter dimension of the bus;
the overlap portion of the bus pattern assigned to the second mask abuts a second portion of the bus pattern assigned to the first mask outside of the overlap portion of the first mask;
the cell layout has an interior region containing a circuit pattern, the circuit pattern is assigned to the first mask, and the overlap portion of the first mask is positioned on a longitudinal edge of the bus pattern distal from the circuit pattern; and
the circuit pattern is positioned at a given distance from a nearest corner of the overlap region, the given distance being smaller than a spacing rule for a distance between patterns.

8. A method, comprising:
providing a non-transitory machine readable storage medium encoded with data representing a cell layout having patterns including a bus pattern, wherein the patterns of the cell layout are assigned into respective sets to be patterned using at least a first mask and a second mask for patterning a single layer of an IC;
assigning a first portion of the bus pattern to be patterned by the first mask and a second portion of the bus pattern to be patterned by the second mask;
assigning an overlap portion of the bus pattern to be patterned by both the first mask and the second mask, including:
assigning a rectangular portion within the bus pattern to the second mask;
assigning a polygon within the bus pattern and surrounding the rectangle on three sides to the first mask, wherein three respective sides of the rectangle overlap with respective overlap portions of the polygon; and

outputting the cell layout to a machine readable storage medium to be read by a system for controlling a process to fabricate the first and second masks for patterning a semiconductor substrate using the first and second masks to pattern a single layer.

9. The method of claim 8 , wherein the cell layout is an odd path cell layout, having a Vdd-Vss path with an odd number of spacings smaller than a minimum single mask separation.

10. The method of claim 8 , wherein:
the cell layout further comprises a second bus pattern assigned to the first mask, with an interior region of the cell layout between the bus pattern and the second bus pattern, and
a portion of the bus pattern assigned to the second mask extends along an interior edge of the bus pattern abutting the interior region.

11. The method of claim 10 , further comprising joining the cell layout vertically with a second cell layout, such that the bus pattern of the cell layout serves as common bus pattern for the cell layout and the second cell layout, wherein the second cell layout is an even path cell layout having an even number of spacings smaller than a minimum single mask separation distance.

12. The method of claim 11 , further comprising:
joining the cell layout horizontally with a third cell layout, such that the bus pattern of the cell layout is continuous with a bus pattern of the third cell layout, and
assigning the bus pattern of the third cell layout to the first mask.

13. The method of claim 12 , wherein:
the cell layout is an odd path cell layout, having a Vdd-Vss path with an odd number of spacings smaller than a minimum single mask separation; and
the third cell layout is an even path cell layout having an even number of spacings smaller than a minimum single mask separation distance.

14. The method of claim 10 , further comprising:
joining the cell layout horizontally with a second cell layout, such that the bus pattern of the cell layout is continuous with a bus pattern of the second cell layout, and
assigning the bus pattern of the second cell layout to the first mask.

15. The method of claim 8 , wherein the cell layout is an odd path cell layout, having a Vdd-Vss path with an odd number of spacings smaller than a minimum single mask separation, the method further comprising:
joining the cell layout vertically with a second cell layout, such that the bus pattern of the cell layout serves as common bus pattern for the cell layout and the second cell layout, wherein the second cell layout is an even path cell layout having an even number of spacings smaller than a minimum single mask separation distance;
joining the cell layout horizontally with a third cell layout, such that the bus pattern of the cell layout is continuous with a bus pattern of the third cell layout, and
assigning the bus pattern of the third cell layout to the first mask.

16. A method, comprising:
providing a non-transitory machine readable storage medium encoded with data representing a cell layout having patterns including a bus pattern, wherein the patterns of the cell layout are assigned into respective sets to be patterned using at least a first mask and a second mask for patterning a single layer of an IC;
assigning a rectangular portion within the bus pattern to the second mask;
assigning a polygon within the bus pattern and surrounding the rectangle on three sides to the first mask, wherein three respective sides of the rectangle overlap with respective overlap portions of the polygon; and
outputting the cell layout to a machine readable storage medium to be read by a system for controlling a process to fabricate the first and second masks for patterning a semicondu

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Hsu Chin-Hsiung
• Chen Huang-Yu
• Wang Chung-Hsing

Classifications

• G06F30/00

  Computer-aided design [CAD] · CPC title

• G06F2119/06

  Power analysis or power optimisation · CPC title

• G06F17/50 Primary

  Physics · mapped topic

• G06F2217/78

  Physics · mapped topic

• G06F17/5072

  Physics · mapped topic