Stitched devices

Patent metadata

Field	Value
Publication number	US-9543192-B2
Application number	US-201514715538-A
Country	US
Kind code	B2
Filing date	May 18, 2015
Priority date	May 18, 2015
Publication date	Jan 10, 2017
Grant date	Jan 10, 2017

Abstract

A stitched device is disclosed. The stitched device includes first and second base devices having first and second stitched interconnects electrically coupled in a stitching level. This enables a single substrate of the stitched device to have electrically coupled first and second base devices.

First claim

What is claimed is:

1. A method of forming a stitched device comprising:
providing a wafer having first and second major surfaces, wherein the first major surface includes a photoresist layer, the first major surface includes a stitching level, wherein the stitching level is an interconnect level of the stitched device;
lithographically processing the stitching level which comprises
exposing the photoresist layer with an exposure source using a first reticle for the stitching level of a first base device at a first position on the wafer, wherein the first reticle includes a first interconnect pattern for first interconnects of a stitching level of the first base device,
exposing the photoresist layer with the exposure source using a second reticle for the stitching level of a second base device at a second position on the wafer, wherein the second reticle includes a second interconnect pattern for second interconnects of a stitching level of the second base device, wherein
adjacent sides of the first and second patterns abut to form common sides of the first and second base device, and
the first and second interconnect patterns include at least one stitching point for coupling a first stitched interconnect with a second stitched interconnect at the common sides; and

processing the wafer to form first and second interconnects in the stitching levels of the first and second base devices, wherein the first stitched interconnect is electrically coupled to the second stitched interconnect at the stitching point.

2. The method of claim 1 wherein the stitched device comprises a stitched integrated circuit with stitched first and second base integrated circuit devices.

3. The method of claim 2 wherein the stitched device comprises additional base devices.

4. The method of claim 2 wherein the stitched device comprises a plurality of stitching levels in a plurality of interconnect levels.

5. The method of claim 2 wherein the stitching level comprises an upper interconnect level with larger design rules.

6. The method of claim 1 wherein the stitched device comprises an interposer with stitched first and second base interposers.

7. The method of claim 6 wherein the stitched interposer comprises additional base interposers.

8. The method of claim 6 wherein the stitching level comprises an interconnect level of a redistribution layer.

9. The method of claim 8 wherein the stitched device comprises a plurality of stitching levels in a plurality of interconnect levels.

10. The method of claim 1 wherein one of the first and second interconnects at the stitching point comprises a stitch coupler, wherein the stitch coupler has a larger width than a width of the interconnects.

11. The method of claim 10 wherein the first and second interconnects at the stitching point comprise stitch couplers.

12. The method of claim 10 wherein the stitching level comprises a plurality of stitching points for coupling a plurality of first interconnects to a plurality of second interconnects.

13. The method of claim 1 wherein lithographically processing comprises shifting exposure of the photoresist layer using the second reticle toward the first position to ensure communication of the first and second stitched interconnect patterns at the stitching point.

14. The method of claim 1 wherein lithographically processing comprises using first and second reticles in which at least adjacent edges of the reticles of the stitched device are increased to ensure communication of the first and second stitched interconnect patterns at the stitching point.

15. A method of forming a stitched device comprising:
providing a wafer having first and second major surfaces, wherein the first major surface includes a photoresist layer, the first major surface includes a stitching level, wherein the stitching level is an interconnect level of the stitched device;
lithographically processing the stitching level which comprises
exposing the photoresist layer with an exposure source using a first reticle for the stitching level of a first base device at a first position on the wafer, wherein the first reticle includes a first interconnect pattern for first interconnects of a stitching level of the first base device,
exposing the photoresist layer with the exposure source using a second reticle for the stitching level of a second base device at a second position on the wafer, wherein the second reticle includes a second interconnect pattern for second interconnects of a stitching level of the second base device, wherein
adjacent sides of the first and second patterns abut to form common sides,
the first and second interconnect patterns include at least one stitching point for coupling a first stitched interconnect with a second stitched interconnect at the common sides, and
wherein at least one of the first and second stitched interconnects at the stitching point comprises a stitch coupler, the stitch coupler has a larger width than a width of the interconnects; and

processing the wafer to form first and second interconnects in the stitching levels of the first and second base devices, wherein the first stitched interconnect is electrically coupled to the second stitched interconnect at the stitching point.

16. The method of claim 15 wherein the stitched device comprises a plurality of stitching levels in a plurality of interconnect levels.

17. The method of claim 1 comprising:
providing a substrate; and
forming through silicon via (TSV) contacts extending through the first major surface of the substrate, wherein the TSV contacts are lined with a dielectric liner.

18. The method of claim 1 wherein the first and second reticles comprise a main region and a frame region surrounding the main region.

19. The method of claim 3 wherein the base devices are formed by different lithographic processes and electrically stitched.

20. The method of claim 8 comprising forming a pad level over the redistribution layer.

Assignees

• Globalfoundries Sg Pte Ltd

Inventors

• Shao Wei
• Tan Juan Boon
• Liu Wei
• Yi Wanbing

Classifications

• H10W90/10

  Configurations of laterally-adjacent chips · CPC title

• H10W70/093

  Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W90/401

  characterised by multiple insulating or insulated package substrates, interposers or RDLs · CPC title

• H10W90/00

  Package configurations · CPC title