Methods for fabricating integrated circuits using multi-patterning processes

Patent metadata

Field	Value
Publication number	US-9530689-B2
Application number	US-201514684949-A
Country	US
Kind code	B2
Filing date	Apr 13, 2015
Priority date	Apr 13, 2015
Publication date	Dec 27, 2016
Grant date	Dec 27, 2016

Abstract

Methods for fabricating integrated circuits are provided. One method includes decomposing a master pattern layout for a semiconductor device layer that includes a target metal line with a target interconnecting via/contact into a first sub-pattern and a second sub-pattern. The target metal line is decomposed into a first line feature pattern that is part of the first sub-pattern and a second line feature pattern that is part of the second sub-pattern such that the first and second line feature patterns have overlapping portions defining a stitch that corresponds to the target interconnecting via/contact. A first photomask is generated that corresponds to the first sub-pattern. A second photomask is generated that corresponds to the second sub-pattern.

First claim

What is claimed is:

1. A method for fabricating an integrated circuit, the method comprising:
patterning a first hard mask layer overlying a dielectric layer of dielectric material that overlies a semiconductor substrate using a first photomask to transfer a first line feature pattern from the first photomask to the first hard mask layer to form a first patterned hard mask layer having a first line feature opening formed therethrough that corresponds to the first line feature pattern and that exposes a first portion of the dielectric layer;
depositing a photoresist layer overlying the first patterned hard mask layer including overlying the first portion of the dielectric layer;
patterning the photoresist layer using a second photomask to transfer a second line feature pattern from the second photomask to the photoresist layer to form a patterned photoresist layer having a second line feature opening formed therethrough that corresponds to the second line feature pattern, wherein patterning the photoresist layer comprises forming the patterned photoresist layer such that the first and second line feature openings partially overlap to expose a first part of the first portion of the dielectric layer; and
transferring the first and second line feature patterns from the first patterned hard mask layer and the patterned photoresist layer to the dielectric layer to form an interconnect-hole that extends through the first part of the first portion of the dielectric layer and a metal line trench that extends laterally in an upper portion of the dielectric layer open to the interconnect-hole, wherein the interconnect-hole extends through a lower portion of the dielectric layer directly below the first part of the metal line trench.

2. The method of claim 1 , wherein transferring the first and second line feature patterns comprises exposing the first part of the first portion of the dielectric layer to a first etching process using the patterned photoresist layer and the first patterned hard mask layer as first etch masks to form a recess through the first part of the dielectric layer.

3. The method of claim 2 , wherein transferring the first and second line feature patterns comprises transferring a non-overlapping portion of the second line feature pattern to the first patterned hard mask layer using a second etching process and the patterned photoresist layer as a second etch mask to form a second patterned hard mask layer having a second line feature opening formed therethrough that corresponds to the non-overlapping portion of the second line feature pattern and that exposes a second portion of the dielectric layer adjacent to the recess on a side opposite a remaining part of the first portion of the dielectric layer.

4. The method of claim 3 , wherein transferring the first and second line feature patterns comprises removing the patterned photoresist layer to expose the remaining part of the first portion of the dielectric layer.

5. The method of claim 4 , wherein transferring the first and second line feature patterns comprises exposing the second portion of the dielectric layer, the recess, and the remaining part of the first portion of the dielectric layer to a third etching process using the second patterned hard mask layer as a third etch mask to form the interconnect-hole and the metal line trench.

6. A method for fabricating an integrated circuit, the method comprising:
patterning a first hard mask layer overlying a dielectric layer of dielectric material that overlies a semiconductor substrate using a first photomask to transfer a first line feature pattern from the first photomask to the first hard mask layer to form a first patterned hard mask layer;
transferring the first line feature pattern from the first patterned hard mask layer to the dielectric layer to form a first metal line trench section extending laterally in an upper portion of the dielectric layer;
conformally depositing a hard mask-forming material overlying the first patterned hard mask layer and the first metal line trench section to form a conformal-coated patterned hard mask layer;
transferring a second line feature pattern from a second photomask to the conformal-coated patterned hard mask layer such that the second line feature pattern partially overlaps a first part of the first metal line trench section to form a second patterned hard mask layer; and
transferring the second line feature pattern from the second patterned hard mask layer to the dielectric layer to form an interconnect-hole that extends through a lower portion of the dielectric layer directly below the first part of the first metal line trench section and a second metal line trench section that extends laterally in the upper portion of the dielectric layer continuous with the first metal line trench section to form a metal line trench that is open to the interconnect-hole.

7. The method of claim 6 , wherein conformally depositing the hard mask-forming material comprises conformally depositing the hard mask-forming material along a sidewall of the upper portion of the dielectric layer proximate the first part of the first metal line trench section.

8. The method of claim 7 , wherein transferring the second line feature pattern to the conformal-coated patterned hard mask layer comprises depositing a photoresist layer overlying the conformal-coated patterned hard mask layer including overlying a sidewall portion of the hard mask-forming material that is disposed along the sidewall of the upper portion of the dielectric layer.

9. The method of claim 8 , wherein transferring the second line feature pattern to the conformal-coated patterned hard mask layer comprises patterning the photoresist layer using the second photomask to transfer the second line feature pattern to the photoresist layer to form a patterned photoresist layer.

10. The method of claim 9 , wherein transferring the second line feature pattern to the conformal-coated patterned hard mask layer comprises etching the conformal-coated patterned hard mask layer using a first etching process and the patterned photoresist layer as a first etch mask to form the second patterned hard mask layer.

11. The method of claim 10 , wherein transferring the second line feature pattern to the dielectric layer comprises exposing a portion of the dielectric layer to a second etching process using the second patterned hard mask layer as a second etch mask to form the second metal line trench section and the interconnect-hole.

12. The method of claim 11 , wherein transferring the second line feature pattern to the dielectric layer comprises removing the sidewall portion of the hard mask-forming material.

Assignees

• Globalfoundries Inc

Inventors

• Civay Deniz Elizabeth
• Stephens Jason Eugene
• Li Jiong
• Bouche Guillaume
• Farrell Richard A

Classifications

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/087

  involving multiple stacked pre-patterned masks · CPC title

• H10W20/069 Primary

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H01L21/76802

  Electricity · mapped topic