Wiring structure and method of forming the same, and semiconductor device including the wiring structure

Patent metadata

Field	Value
Publication number	US-2016379891-A1
Application number	US-201615187901-A
Country	US
Kind code	A1
Filing date	Jun 21, 2016
Priority date	Jun 29, 2015
Publication date	Dec 29, 2016
Grant date	—

Abstract

In a method of forming a wiring structure, a first mask having a first opening including a first portion extending in a second direction and a second portion extending in a first direction is formed. A second mask including a second opening overlapping the first portion of the first opening and third openings each overlapping the second portion of the first opening is designed. The second mask is fabricated to include a fourth opening by enlarging the second opening. The fourth opening overlaps a boundary between the first and second portions of the first opening. An insulating interlayer is etched using the first and second masks to form first and second via holes corresponding to the fourth and third openings, and a trench corresponding to the first opening. First and second vias and a wiring are formed to fill the first and second via holes and the trench.

First claim

1 - 20 . (canceled)

21 . A semiconductor device, comprising:
an insulating interlayer on a substrate; a wiring in an upper portion of the insulating interlayer, the wiring including a first portion and a second portion, the second portion extending in a first direction, the first portion extending in a second direction, the second portion crossing the second direction and being connected to the first portion, and a corner of the wiring at which the first and second portions are connected to each other having a rounded shape; and a via structure in a lower portion of the insulating interlayer, the via structure including,
first vias in a first region at a first density, at least one of the first vias contacting a bottom of the first portion of the wiring; and
second vias in a second region at a second density that is greater than the first density, at least one of the second vias contacting a bottom of the second portion of the wiring,
wherein the at least one of the first vias contacting the bottom of the first portion of the wiring at least partially contacts the rounded corner of the wiring.

22 . The semiconductor device of claim 21 , wherein, in a plan view, the at least one of the first vias has a corner with a rounded shape corresponding to the rounded shape of the corner of the wiring.

23 . The semiconductor device of claim 21 , wherein the rounded corner of the wiring includes a protrusion protruding therefrom in a plan view.

24 . The semiconductor device of claim 23 , wherein the at least one of the first vias is adjacent to the protrusion of the rounded corner of the wiring, and does not contact a bottom of the protrusion.

25 . The semiconductor device of claim 21 , wherein, in a plan view, an area of the at least one of the first vias contacting the bottom of the first portion of the wiring is equal to or greater than an area of the at least one of the second vias contacting the bottom of the second portion of the wiring.

26 . The semiconductor device of claim 21 , wherein the second density is equal to or more than about ten times the first density.

27 . The semiconductor device of claim 21 , wherein the first and second directions cross each other at a substantially right angle.

28 . The semiconductor device of claim 21 , wherein the at least one of the first vias contacting the bottom of the first portion of the wiring includes a first metal pattern and a first barrier pattern covering a bottom and a sidewall of the first metal pattern,
the at least one of the second vias contacting the bottom of the second portion of the wiring includes a second metal pattern and a second barrier pattern covering a bottom and a sidewall of the second metal pattern, and wherein the wiring includes a third metal pattern and a third barrier pattern covering a portion of a bottom and a sidewall of the third metal pattern.

29 . The semiconductor device of claim 28 , wherein the first to third barrier patterns include a substantially same material, and the first to third metal patterns include a substantially same material.

30 . A semiconductor device, comprising:
an active fin on a substrate, the active fin partially protruding from an isolation pattern on the substrate and extending in a first direction; a gate structure on the active fin and the isolation pattern, the gate structure extending in a second direction crossing the first direction; a source/drain layer on a portion of the active fin adjacent to the gate structure; a contact plug on the source/drain layer; a first insulating interlayer structure containing the gate structure, the source/drain layer and the contact plug; a second insulating interlayer on the first insulating interlayer structure; a wiring in an upper portion of the second insulating interlayer, the wiring including a first portion and a second portion, the second portion extending in a third direction. the first portion extending in a fourth direction, the second portion crossing the fourth direction and being connected to the first portion, and a corner of the wiring at which the first and second portions are connected to each other having a rounded shape; and a via structure in a lower portion of the second insulating interlayer, the via structure including:
first vias in a first region at a first density, at least one of the first vias contacting a bottom of the first portion of the wiring; and
second vias in a second region at a second density that is greater than the first density, at least one of the second vias contacting a bottom of the second portion of the wiring,
wherein the at least one of the first vias at least partially contacts the bottom of the first portion of the wiring contacts the rounded corner of the wiring.

31 . The semiconductor device of claim 30 , wherein, in a plan view, the at least one of the first vias has a corner with a rounded shape corresponding to the rounded shape of the corner of the wiring.

32 . The semiconductor device of claim 30 , wherein the rounded corner of the wiring includes a protrusion protruding therefrom in a plan view.

33 . The semiconductor device of claim 32 , wherein the at least one of the first vias is adjacent to the protrusion of the rounded corner of the wiring, but does not contact a bottom of the protrusion.

34 . The semiconductor device of claim 30 , wherein, in a plan view, an area of the at least one of the first vias contacting the bottom of the first portion of the wiring is equal to or greater than an area of the at least one of the second vias contacting the bottom of the second portion of the wiring.

35 . The semiconductor device of claim 30 , wherein the first and third directions are substantially parallel to each other, the second and fourth directions are substantially parallel to each other, and the first and second directions cross each other at a substantially right angle.

36 . A semiconductor device, comprising:
an insulating interlayer on a substrate; a wiring in the insulating interlayer, the wiring including a first portion extending in a first direction, a second portion extending in a second direction, and a bent portion connecting the first portion and the second portion; and a via structure in the insulating interlayer between the wiring and the substrate, the via structure including,
at least one first via in contact with the first portion of the wiring and at least partially in contact with the bent portion of the wiring; and
at least one second via in contact with the second portion of the wiring.

37 . The semiconductor device of claim 36 , wherein the second direction is substantially perpendicular to the first direction, and the bent portion is arcuate.

38 . The semiconductor device of claim 36 , wherein
the via structure includes a plurality of first vias and a plurality of second vias; the first vias are at a first density; and the second vias are at a second density greater than the first density.

39 . The semiconductor device of claim 36 , wherein the first and second directions are substantially parallel to a surface of the substrate.

40 . The semiconductor device of claim 36 , wherein
the at least one first via has a via bent portion corresponding to the bent portion of the wiring in a direction substantially parallel to a surface of the substrate; the bent portion of the wiring includes a protrusion protruding therefrom in a direction substantially parallel to a surface of the substrate; and
the at least one first via i

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Jin-Hyeung
• Kim Yeon-Joo
• Kim In-Hwan
• Kim Jun-Jung
• Park Kyoung-Pil
• Ahn Jeong-Hoon
• Lee Sang-Chul
• Lee Joon-Nyung
• Lee Hyo-Seon

Classifications

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/088

  involving partial etching of via holes · CPC title

• H10W20/087

  involving multiple stacked pre-patterned masks · CPC title

• H10W20/43

  Layouts of interconnections · CPC title