System, method and computer-accessible medium for providing secure split manufacturing

Patent metadata

Field	Value
Publication number	US-10423749-B2
Application number	US-201414775164-A
Country	US
Kind code	B2
Filing date	Mar 14, 2014
Priority date	Mar 14, 2013
Publication date	Sep 24, 2019
Grant date	Sep 24, 2019

Abstract

Exemplary systems, methods and computer-accessible mediums can secure split manufacturing of an integrated circuit by modifying a previous location of at least one pin to a further location of the at least one pin based on a fault analysis procedure. A determination of the further location can include an iterative procedure that can be a greedy iterative procedure. The modification of the location of the at least one partition pin can be performed by swapping at least one further partition pin with the at least one partition pin.

First claim

What is claimed is:

1. A non-transitory computer-accessible medium having stored thereon computer-executable instructions for providing or securing split manufacturing of an integrated circuit (“IC”), wherein, when a computer hardware arrangement executes the instructions, the computer arrangement is configured to perform procedures comprising:
receiving information related to a design of the IC;
determining at least one first partition pin in the design located at a first location and at least one second partition pin in the design located at a second location to be swapped based on a fault analysis procedure that identifies at least one IC output, wherein the at least one first partition pin and the at least one second partition pin are interconnected with one another based on at least one metal layer; and
swapping the at least one first partition pin with the at least one second partition pin in the design.

2. The computer-accessible medium of claim 1 , wherein the computer arrangement is further configured to determine the second location using an iterative procedure.

3. The computer-accessible medium of claim 2 , wherein the iterative procedure comprises a greedy iterative procedure.

4. The computer-accessible medium of claim 1 , wherein the computer arrangement is further configured to determine the second location based on an effect of swapping the at least one first partition pin and the at least one second partition pin on a maximum number of outputs of the IC.

5. The computer-accessible medium of claim 1 , wherein the computer arrangement is further configured to determine at least one further pair of pins to swap based on an effect of the swapping as a function of a maximum number of outputs.

6. The computer-accessible medium of claim 1 , wherein the computer arrangement is further configured to determine the second location based, at least in part, on a Hamming Distance.

7. The computer-accessible medium of claim 6 , wherein the Hamming Distance is approximately 50% between a plurality of outputs of an original netlist of the design and a deceiving netlist of the design.

8. The computer-accessible medium of claim 1 , wherein the computer arrangement is further configured to determine the second location based, at least in part, on an Avalanche Criterion.

9. The computer-accessible medium of claim 1 , wherein the at least one metal layer is at least one Front End Of Line (FEOL) metal layer, wherein connections inside at least one partition are made on at least one Back End Of Line (BEOL) metal layer, and wherein the at least one FEOL and the at least one BEOL layers are manufactured separately.

10. The computer-accessible medium of claim 1 , wherein the computer arrangement is further configured to determine the second location using a netlist.

11. The computer-accessible medium of claim 10 , wherein the computer arrangement is further configured to identify the second location in the netlist using a cumulative sum of corrupted output bits over a set of random test patterns.

12. The computer-accessible medium of claim 1 , wherein the computer arrangement is further configured to deceive an attacker into making at least one wrong connection between at least one of the at least one first partition pin or the at least one second partition pin based on a reverse engineered Back End Of Line (BEOL) netlist with missing Front End Of Line (FEOL) connections.

13. The method of claim 1 , wherein the second location is determined based, at least in part, on at least one of a Hamming Distance or an Avalanche Criterion.

14. The method of claim 13 , wherein the Hamming Distance is approximately 50% between a plurality of outputs of an original netlist of the design and a deceiving netlist of the design.

15. The computer-accessible medium of claim 1 , wherein the computer arrangement is further configured to utilize the fault analysis procedure to determine a fault impact value for each of a plurality of candidate partition pins to swap.

16. The computer-accessible medium of claim 15 , wherein the fault impact value is based on a cumulative sum of bits corrupted by the candidate partition pins over a set of random test patterns.

17. A method providing or securing split manufacturing of an integrated circuit (“IC”), comprising:
receiving information related to a design of the IC;
determining at least one first partition pin in the design located at a first location and at least one second partition pin in the design located at a second location to be swapped based on a fault analysis procedure that identifies at least one IC output, wherein the at least one first partition pin and the at least one second partition pin are interconnected with one another based on at least one metal layer; and
using a computer hardware arrangement, swapping the at least one first partition pin with the at least one second partition pin in the design.

18. The method of claim 17 , further comprising determining the second location using an iterative procedure.

19. The method of claim 18 , wherein the iterative procedure comprises a greedy iterative procedure.

20. The method of claim 17 , further comprising, determining a fault impact value for each of a plurality of candidate partition pins to swap using the fault analysis procedure.

21. The method of claim 20 , wherein the fault impact value is based on a cumulative sum of bits corrupted by the candidate partition pins over a set of random test patterns.

22. An integrated circuit (IC), comprising:
at least one first partition pin provided in the IC whose location has been swapped with at least one second partition pin provided in the IC based on a fault analysis procedure that identifies at least one IC output affected by the swap, wherein the at least one first partition pin and the at least one second partition pin are interconnected with one another based on at least one metal layer.

23. The IC of claim 22 , wherein the fault analysis procedure is used to determine a fault impact value for each of a plurality of candidate partition pins to swap.

24. The IC of claim 23 , wherein the fault impact value is based on a cumulative sum of bits corrupted by the candidate partition pins over a set of random test patterns.

Assignees

• Univ New York

Inventors

• Rajendran Jeyavijayan
• Sinanoglu Ozgur
• Karri Ramesh

Classifications

• G06F30/39 Primary

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• G06F30/398

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F21/75

  by inhibiting the analysis of circuitry or operation · CPC title

• G06F17/5072 Primary

  Physics · mapped topic

• G06F17/5081

  Physics · mapped topic