Testing integrated circuits during split fabrication

Patent metadata

Field	Value
Publication number	US-2016341786-A1
Application number	US-201515112369-A
Country	US
Kind code	A1
Filing date	Jan 21, 2015
Priority date	Jan 22, 2014
Publication date	Nov 24, 2016
Grant date	—

Abstract

In one aspect, a method comprises providing at least two identical front-end-of-line (FEOL) portions of an integrated circuit (IC) in a single wafer, with at least some of each FEOL portion comprising a plurality of circuit elements; building a design back-end-of-line (BEOL) portion of the IC on at least one of the FEOL portions to form a product chip, with the design BEOL portion configuring design-type interconnections of the same plurality of circuit elements for a first instantiation; building a test-only BEOL structure on at least one of the FEOL portions to form a sacrificial test device, with the test-only BEOL structure configuring test-type interconections of the same plurality of circuit elements for a second instantiation; and testing the sacrificial test device for at least one of functionality or reliability.

First claim

What is claimed is:

1 . A method comprising:
providing at least two identical front-end-of-line (FEOL) portions of an integrated circuit (IC) in a single wafer, with at least some of each FEOL portion comprising a plurality of circuit elements; building a design back-end-of-line (BEOL) portion of the IC on at least one of the FEOL portions to form a product chip, with the design BEOL portion configuring design-type interconnections of the same plurality of circuit elements for a first instantiation; building a test-only BEOL structure on at least one of the FEOL portions to form a sacrificial test device, with the test-only BEOL structure configuring test-type interconnections of the same plurality of circuit elements for a second instantiation; and testing the sacrificial test device for at least one of functionality or reliability.

2 . The method of claim 1 , wherein building the test-only BEOL structure on the FEOL portion comprises building the test-only BEOL structure on the FEOL portion using a split fabrication process.

3 . The method of claim 2 , further comprising:
after completion of the manufacturing of the FEOL portion of the IC, generating a test-only BEOL design using a set of values for control parameters, where the set of values is selected from a plurality of sets of values for the control parameters, with each of the plurality of sets of values generating a different test-only BEOL design for the FEOL portion, wherein building the test-only BEOL structure on the FEOL portion comprises building the test-only BEOL structure on a randomly selected sacrificial die of the wafer containing the FEOL portion using the generated test-only BEOL design.

4 . The method of claim 1 , wherein the plurality of circuit elements comprises a plurality of logic gates, and testing the sacrificial test device comprises testing the sacrificial test device for at-speed function of every logic gate of the plurality of logic gates.

5 . The method of claim 4 , wherein the test-only BEOL structure configures the test-type interconnections of the same plurality of logic gates so that all of the plurality of logic gates are part of at least one path that is within 5% of a longest path delay of the IC.

6 . The method of claim 4 , wherein the test-only BEOL structure configures the test-type interconnections of the same plurality of logic gates so that a number of paths is proportional to a number of the plurality of logic gates as a function of the logic depth.

7 . The method of claim 4 , wherein the test-only BEOL structure configures the test-type interconnections of the same plurality of logic gates so that each of the plurality of logic gates is driven by one time varying input.

8 . The method of claim 1 , wherein the plurality of circuit elements comprises a plurality of logic gates, and the test-only BEOL structure configures the same plurality of logic gates as one or more ring oscillators (ROs).

9 . The method of claim 7 , wherein two or more of the ROs have a same delay.

10 . The method of claim 1 , wherein the plurality of circuit elements comprise a plurality of flip-flops, and the test-only BEOL structure configures the plurality of flip-flops as frequency dividers or counters.

11 . A device comprising:
at least two identical front-end-of-line (FEOL) portions of an integrated circuit (IC) in a single wafer, with each of the FEOL portions comprising a plurality of circuit elements; a design back-end-of-line (BEOL) portion of the IC built on at least one of the FEOL portions to form a product chip, with the design BEOL portion configuring design-type interconnections of the same plurality of circuit elements for a first instantiation; and a test-only BEOL structure built on at least one of the FEOL portions to form a sacrificial test device, with the test-only BEOL structure configuring test-type interconnections of the same plurality of circuit elements for a second instantiation to allow testing of the sacrificial test device for at least one of functionality or reliability.

12 . The device of claim 11 , wherein the test-only BEOL structure is built on the FEOL portion using a split fabrication process.

13 . The method of claim 12 , wherein the test-only BEOL structure is built on a randomly selected sacrificial die of the wafer containing the FEOL portion according to a test-only BEOL design, with the test-only BEOL design generated after completion of the manufacturing of the FEOL portion of the IC using a set of values for control parameters, where the set of values is selected from a plurality of sets of values for the control parameters, with each of the plurality of sets of values generating a different test-only BEOL design for the FEOL portion.

14 . The method of claim 11 , wherein the plurality of circuit elements comprises a plurality of logic gates, and the test-only BEOL structure allows testing of the device for at-speed function of every logic gate of the plurality of logic gates.

15 . The method of claim 14 , wherein the test-only BEOL structure configures the test-type interconnections of the same plurality of logic gates so that all of the plurality of logic gates are part of at least one path that is within 5% of a longest path delay of the IC.

16 . The method of claim 14 , wherein the test-only BEOL structure configures the test-type interconnections of the same plurality of logic gates so that a number of paths is proportional to a number of the plurality of logic gates as a function of the logic depth.

17 . The method of claim 14 , wherein the test-only BEOL structure configures the test-type interconnections of the same plurality of logic gates so that each of the plurality of logic gates is driven by one time varying input.

18 . The method of claim 11 , wherein the plurality of circuit elements comprises a plurality of logic gates, and the test-only BEOL structure configures the same plurality of logic gates as one or more ring oscillators (ROs).

19 . The method of claim 17 , wherein two or more of the ROs have a same delay.

20 . The method of claim 11 , wherein the plurality of circuit elements comprise a plurality of flip-flops, and the test-only BEOL structure configures the plurality of flip-flops as frequency dividers or counters.

Assignees

• Univ Carnegie Mellon

Inventors

• Pileggi Lawrence
• Das Bishnu P
• Vaidyanathan Kaushik

Classifications

• G01R31/2818 Primary

  using test structures on, or modifications of, the card under test, made for the purpose of testing, e.g. additional components or connectors (G01R31/2805 takes precedence; printed circuits having, e.g. symbols, test patterns or visualisation means H05K1/0266) · CPC title