Integrated circuit design changes using through-silicon vias

Patent metadata

Field	Value
Publication number	US-9501603-B2
Application number	US-201414477976-A
Country	US
Kind code	B2
Filing date	Sep 5, 2014
Priority date	Sep 5, 2014
Publication date	Nov 22, 2016
Grant date	Nov 22, 2016

Abstract

A method for adding an electrical interconnection within a three-dimensional integrated circuit (3-D IC) is disclosed. The method may include creating, within a design file of a 3-D IC that specifies a layout for a first chip of the 3-D IC, design data corresponding to a set of through-silicon via (TSV) reservation areas. The method may also include receiving an engineering change order (ECO) and releasing, in response to the ECO, at least one TSV reservation area for reuse. The method may also include adding, by re-using at least one TSV reservation area, an electrical interconnection within the design file of the first chip of the 3-D IC.

First claim

What is claimed is:

1. A computer program product for adding an electrical interconnection within a three-dimensional integrated circuit (3-D IC), the computer program product comprising:
a non-transitory computer readable storage medium having stored thereon:
program instructions executable by one or more processor circuits to cause the one or more processor circuits to:
create, within a design file of a first chip of the 3-D IC, design data corresponding to a set of through-silicon via (TSV) reservation areas;
receive an engineering change order (ECO);
release, in response to the ECO, at least one TSV reservation area of the set of TSV reservation areas; and
create within the design file, design data specifying at least one TSV, said at least one TSV creating an electrical interconnection within the first chip of the 3-D IC, and

said program instructions are executable to further cause the one or more processor circuits to create a region of locations wherein each of the locations has a distance, from signal nets belonging to at least one of a group of types consisting of: data, control logic, clock and power distribution, that is less than or equal to a specified maximum distance, and to place at least one TSV reservation area of the set of TSV reservation areas within the region, and
to create, in response to a ratio of a number of signal nets to a number of TSV reservation areas and within the region of locations, design data corresponding to a number of TSV reservation areas.

2. The computer program product of claim 1 , wherein the program instructions are executable to further cause the one or more processor circuits to create, in at least one of the set of TSV reservation areas, design data corresponding to at least one spare TSV that is not electrically connected to other components of the 3-D IC within the design file.

3. The computer program product of claim 1 , wherein design data corresponding to the set of TSV reservation areas includes at least one layer set of a group of layer sets consisting of: front-end-of-line (FEOL) layers and back end of line (BEOL) layers.

4. The computer program product of claim 1 , wherein the program instructions are executable to further cause the one or more processor circuits to release, for use in routing, in response to a specification within the ECO of additional routing area, at least one of the TSV reservation areas.

5. A system for adding an electrical interconnection within a three-dimensional integrated circuit (3-D IC) design file having a first chip with a plurality of TSV reservation areas and a second chip, the system comprising:
one or more processor circuits configured to:
create, within a design file of a first chip of the 3-D IC, design data corresponding to a set of through-silicon via (TSV) reservation areas;
receive an engineering change order (ECO);
release, in response to the ECO, at least one TSV reservation area of the set of TSV reservation areas; and
create within the design file, design data specifying at least one TSV, said at least one TSV creating an electrical interconnection within the first chip of the 3-D IC, and
create a region of locations wherein each of the locations has a distance, from signal nets belonging to at least one of a group of types consisting of: data, control logic, clock and power distribution, that is less than or equal to a specified maximum distance, and to place at least one TSV reservation area of the set of TSV reservation areas within the region, and
create, in response to a ratio of a number of signal nets to a number of TSV reservation areas and within the region of locations, design data corresponding to a number of TSV reservation areas.

6. The system of claim 5 , wherein the one or more processor circuits are further configured to release, for use in creating circuits, in response to a specification within the ECO of additional circuit area, at least one of the TSV reservation areas.

7. The system of claim 5 , wherein the one or more processor circuits are further configured to release a TSV previously allocated for power distribution.

8. The system of claim 5 , wherein the one or more processor circuits are further configured to create, in response to a specification within the ECO of a new TSV interconnection between the first chip and the second chip of the 3-D IC, design data corresponding to a TSV in a TSV reservation area within the first chip.

9. The system of claim 5 , wherein the one or more processor circuits are further configured to create, in response to receiving the ECO after processing of interconnect layers below a capture layer, and in a TSV reservation area, design data corresponding to a spare TSV connected to one of a power net and a ground net.

10. The system of claim 5 , wherein the one or more processor circuits are further configured to release, for reallocation, in response to a specification within the ECO of reallocating a first TSV reservation area having a first footprint area to a plurality of TSV reservation areas each having a footprint area smaller than the first footprint area, at least one of the TSV reservation areas.

Assignees

• IBM

Inventors

• Barowski Harry
• Keinert Joachim
• Rangarajan Sridhar H
• Ren Haoxing
• Saha Sourav

Classifications

• G06F30/394 Primary

  Routing (G06F30/396 takes precedence) · CPC title

• G06F17/5077 Primary

  Physics · mapped topic