System, method and computer-accessible medium for facilitating logic encryption

Patent metadata

Field	Value
Publication number	US-2016034694-A1
Application number	US-201414775138-A
Country	US
Kind code	A1
Filing date	Mar 14, 2014
Priority date	Mar 14, 2013
Publication date	Feb 4, 2016
Grant date	—

Abstract

Exemplary systems, methods and computer-accessible mediums for encrypting at least one integrated circuit (IC) can include determining, using an interference graph, at least one location for a proposed insertion of at least one gate in or at the at least one IC, and inserting the gate(s) into the IC(s) at the location(s). The interference graph can be constructed based at least in part on an effect of the location(s) on at least one further location of the IC(s).

First claim

What is claimed is:

1 . A non-transitory computer-accessible medium having stored thereon computer-executable instructions for encrypting at least one integrated circuit (“IC”), wherein, when a computer hardware arrangement executes the instructions, the computer arrangement is configured to perform procedures comprising:
determining, using an interference graph, at least one location for a proposed insertion of at least one gate in or at the at least one IC; and
inserting the at least one gate into the at least one IC at or in the at least one location.

2 . The computer-accessible medium of claim 1 , wherein the computer arrangement is further configured to construct the interference graph based at least in part on an effect of the at least one location on at least one further location of the at least one IC.

3 . The computer-accessible medium of claim 2 , wherein the computer arrangement is further configured to generate at least one graph node related to the at least one location and at least one graph edge related to a degree of erasability of an effect of the at least one location in or on the at least one further location.

4 . The computer-accessible medium of claim 3 , wherein the computer arrangement is further configured to assign a first weight to at least one non-mutable edge and a second weight at least one mutable edge.

5 . The computer-accessible medium of claim 4 , wherein the first weight is higher than the second weight.

6 . The computer-accessible medium of claim 3 , wherein the computer arrangement is further configured to select at least one key-gate based on the at least one gate that maximizes a sum of weights of the at least one graph edge.

7 . The computer-accessible medium of claim 6 , wherein the computer arrangement is further configured to update the interference graph based on the at least one key-gate.

8 . The computer-accessible medium of claim 6 , wherein the at least one key-gate is at least one of an XOR gate or an XNOR gate.

9 . The computer-accessible medium of claim 1 , wherein the determination procedure includes a performance of a clique analysis on the interference graph to determine the at least one location.

10 . The computer-accessible medium of claim 9 , wherein cliques of the clique analysis have a specific size so as to enhance the encryption of the at least one IC.

11 . The computer-accessible medium of claim 1 , wherein the at least one gate is configured to corrupt a functionality of the circuit upon an application of an incorrect key.

12 . A method for encrypting at least one integrated circuit (IC) comprising:
determining, using an interference graph, at least one location for a proposed insertion of at least one gate in or at the at least one IC; and using a computer hardware arrangement, inserting the at least one gate into the at least one IC in or at the at least one location.

13 . The method of claim 12 , further comprising constructing the interference graph based at least in part on an effect of the at least one location on at least one further location of the at least one IC.

14 . The method of claim 13 , further comprising generating at least one graph node related to the at least one location and at least one graph edge related to a degree of erasability of an effect of the at least one location in or on the at least one further location.

15 . The method of claim 14 , wherein the computer-processing arrangement is further configured to assign a first weight to at least one non-mutable edge and a assign second weight at least one mutable edge.

16 . The method of claim 15 , wherein the first weight is higher than the second weight.

17 . The computer-accessible medium of claim 14 , further comprising selecting at least one key-gate based on the at least one gate that maximizes a sum of weights of the at least one graph edge.

18 . The method of claim 17 , further comprising updating the interference graph based on the at least one key-gate.

19 . The method of claim 12 , wherein the determination procedure includes a performance of a clique analysis on the interference graph to determine the at least one location.

20 . An integrated circuit comprising:
at least one gate having a location determined based on an interference graph.

Assignees

• Univ New York

Inventors

• Rajendran Jeyavijayan
• Pino Youngok
• Sinanoglu Ozgur
• Karri Ramesh

Classifications

• H04L9/002

  Countermeasures against attacks on cryptographic mechanisms (network architectures or network communication protocols for protection against malicious traffic H04L63/1441) · CPC title

• G06F2221/2111

  Location-sensitive, e.g. geographical location, GPS · CPC title

• H04L2209/04

  Masking or blinding · CPC title

• G09C1/00

  Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system (cryptographic typewriters G09C3/00) · CPC title

• G06F21/72 Primary

  in cryptographic circuits · CPC title