System and Method for Dual-Region Singulation

Patent metadata

Field	Value
Publication number	US-2016276233-A1
Application number	US-201514660753-A
Country	US
Kind code	A1
Filing date	Mar 17, 2015
Priority date	Mar 17, 2015
Publication date	Sep 22, 2016
Grant date	—

Abstract

A method for semiconductor fabrication includes forming a first array of semiconductor circuitry and a second array of semiconductor circuitry separated by a singulation region and a contact region. The method also includes forming a first array of process control monitoring structures within the singulation region of a substrate. The method also includes forming a first array of contact pads disposed in the contact region. The method also includes forming electrical connections between the first array of process control monitoring structures and the first array of contact pads, wherein all external electrical connections to the first array of process control monitoring structures are made through the first array of contact pads.

First claim

What is claimed is:

1 . A semiconductor die comprising:
a semiconductor circuit; a conductive contact pad; and a floating electrical path ending at a singulated edge of the die, wherein the electrical path is electrically coupled to the conductive contact pad.

2 . The semiconductor die of claim 1 , wherein the floating electrical path comprises a polysilicon path.

3 . The semiconductor die of claim 1 , wherein the floating electrical path comprises a substrate material of the semiconductor circuit.

4 . The semiconductor die of claim 1 , wherein the floating electrical path comprises at least one of aluminum, copper, titanium, tungsten, cobalt, platinum, palladium, molybdenum, nickel, vanadium, silver, gold, aluminum, a metal silicide, and a metal nitride.

5 . The semiconductor die of claim 1 , wherein the conductive contact pad comprises at least one of aluminum, copper, titanium, tungsten, cobalt, platinum, palladium, molybdenum, nickel, vanadium, silver, gold, aluminum, a metal silicide, and a metal nitride.

6 . The semiconductor die of claim 1 , wherein the semiconductor circuit comprises at least one of a metal oxide semiconductor field-effect transistor (MOSFET), a bipolar transistor, an insulated-gate bipolar transistor (IGBT), a diode, a sensor, and an integrated circuit.

7 . A method for semiconductor fabrication, the method comprising:
forming a first array of semiconductor circuitry and a second array of semiconductor circuitry separated by a singulation region of a substrate and a contact region, wherein the contact region and the singulation region of the substrate do not overlap; forming a first array of process control monitoring structures within the singulation region; forming a first array of contact pads disposed in the contact region; and forming electrical connections between the first array of process control monitoring structures and the first array of contact pads, wherein all external electrical connections to the first array of process control monitoring structures are made through the first array of contact pads.

8 . The method of claim 7 , further comprising:
forming a third array of semiconductor circuitry separated from the second array of semiconductor circuitry by another singulation region, wherein a distance between the first array of semiconductor circuitry and the second array of semiconductor circuitry is larger than a distance between the second array of semiconductor circuitry and the third array of semiconductor circuitry.

9 . The method of claim 7 , further comprising:
forming a third array of semiconductor circuitry separated from the second array of semiconductor circuitry by another singulation region and another contact region, wherein a distance between the first array of semiconductor circuitry and the second array of semiconductor circuitry is about the same as a distance between the second array of semiconductor circuitry and the third array of semiconductor circuitry.

10 . The method of claim 7 , further comprising:
performing an electrical parametric test by contacting a test probe at a contact pad of the first array of contact pads; and singulating the substrate through the singulation region after performing the electrical parametric test.

11 . The method of claim 7 , wherein each contact pad in the first array of contact pads comprises at least one of aluminum, copper, titanium, tungsten, cobalt, platinum, palladium, molybdenum, nickel, vanadium, silver, gold, aluminum, a metal silicide, and a metal nitride.

12 . The method of claim 7 , wherein each process control monitoring structure in the first array of process control monitoring structures comprises at least one of a capacitor, resistor, diode, metal oxide semiconductor field-effect transistor (MOSFET), bipolar transistor, insulated-gate bipolar transistor (IGBT), heater, layer stack, isolation check structure, reliability test structure, and contact resistance structure.

13 . The method of claim 7 , wherein the electrical connections between the first array of process control monitoring structures and the first array of contact pads comprises at least one semiconductor connection.

14 . The method of claim 13 , wherein the at least one semiconductor connection comprises at least one of:
polysilicon; and a material that is the same as the substrate.

15 . A method for semiconductor fabrication, the method comprising:
forming a process control monitoring (PCM) structure in a semiconductor wafer comprising a complete set of singulation regions for singulating through the semiconductor wafer, wherein the PCM structure is disposed within the complete set; forming a conductive contact pad in the semiconductor wafer, wherein
the conductive contact pad is electrically coupled to the PCM structure, and
the conductive contact pad is not disposed within the complete set; and
singulating the semiconductor wafer only within the complete set of singulation regions.

16 . The method of claim 15 , further comprising:
performing an electrical parametric test by contacting at the conductive contact pad a probe tip of a testing equipment for the PCM structure, wherein the performing the electrical parametric test occurs prior to the singulating the semiconductor wafer.

17 . The method of claim 15 , wherein any metal structures disposed in the complete set of singulation regions and electrically coupled to the PCM structure are not wider than 20 μm.

18 . The method of claim 17 , wherein any metal structures disposed in the complete set of singulation regions and electrically coupled to the PCM structure comprise a width thinner than a probe tip of a testing equipment for the PCM structure.

19 . The method of claim 15 , wherein
the singulating cuts through the PCM structure but not the contact pad.

20 . The method of claim 15 , wherein the PCM structure is disposed adjacent to the conductive contact pad.

21 . The method of claim 15 , wherein the PCM structure is disposed between semiconductor circuits of the wafer.

22 . The method of claim 15 , wherein the conductive contact pad is formed from a metallization layer of the semiconductor wafer.

23 . A method for layout generation, the method comprising:
obtaining a layout location of a singulation region for singulating through a semiconductor wafer, wherein the layout location is comprised in a layout representing the semiconductor wafer; obtaining a design for a process control monitoring (PCM) structure; and selecting an arrangement for the layout, wherein the arrangement comprises:
a first array of PCM structures each arranged in accordance with the design for the PCM structure, wherein the first array of PCM structures is disposed within the singulation region;
a first array of contact pads disposed in a contact region;
a first array of semiconductor circuitry and a second array of semiconductor circuitry separated by the singulation region and the contact region; and
electrical connections between the first array of PCM structures and the first array of contact pads, wherein all external electrical connections to the first array of PCM structures are made through the first array of contact pads.

24 . The method of claim 23 , wherein each PCM structure in the first array of PCM structures is adjacent to at least one contact pad in the first array of contact pads.

25 . The method of claim 23 ,

Assignees

• Infineon Technologies Austria Ag

Inventors

• Wood Andrew Christopher Graeme
• Fasching Gernot
• Bodea Marius Aurel
• Ostermann Thomas Krotscheck
• Bacher Erwin

Classifications

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• H10P74/273 Primary

  Interconnections for measuring or testing, e.g. probe pads · CPC title

• H10P74/207

  Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics · CPC title

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title