Molded substrate package in fan-out wafer level package

Patent metadata

Field	Value
Publication number	US-10403580-B2
Application number	US-201715858103-A
Country	US
Kind code	B2
Filing date	Dec 29, 2017
Priority date	Dec 29, 2017
Publication date	Sep 3, 2019
Grant date	Sep 3, 2019

Abstract

An electronic device may include a semiconductor die. The electronic device may include a first routing layer. The first routing layer may be coupled to the semiconductor die. A first plurality of routing traces may be in electrical communication with the semiconductor die. The first plurality of routing traces may be positioned within a first routing footprint. The first routing footprint may have a width greater than a width of the semiconductor die.
A second routing layer may be coupled to the first routing layer. A second plurality of routing traces may be in electrical communication with the first plurality of routing traces. The second plurality of routing traces may be positioned within a second routing footprint. The second routing footprint may have a width greater than the width of the first routing footprint.

First claim

The claimed invention is:

1. An electronic device, comprising:
a semiconductor die having a first surface and a second surface, wherein the second surface includes die interconnects;
a first routing layer coupled to the die interconnects of the semiconductor die, the first routing layer including:
a first substrate,
a first plurality of routing traces in electrical communication with the semiconductor die, wherein the first plurality of routing traces are positioned within a first routing footprint and the first routing footprint has a width greater than a width of the semiconductor die;
a second routing layer coupled to the first routing layer, the second routing layer including:
a second substrate,
a second plurality of routing traces in electrical communication with the first plurality of routing traces, wherein the second plurality of routing traces are positioned within a second routing footprint, and
wherein the second routing footprint has a width greater than the width of the first routing footprint;
a first molding material forming a direct interface with the first substrate and enclosing a portion of the semiconductor die; and
a second molding material forming a direct interface with the first molding material and the second substrate, wherein the first surface of the semiconductor die, the first molding material, and the second molding material are coplanar.

2. The electronic device of claim 1 , further comprising a third routing layer, including:
a third substrate, and
a third plurality of wiring traces in electrical communication with either the first plurality of routing traces or the second plurality of routing traces.

3. The electronic device of claim 1 , wherein the first substrate is molded over the first plurality of routing traces.

4. The electronic device of claim 1 , wherein the second routing layer is a fan out wafer level package.

5. The electronic device of claim 1 , wherein the first surface of the semiconductor die is exposed.

6. The electronic device of claim 1 , further comprising one or more solder balls coupled to the second routing layer.

7. The electronic device of claim 1 , wherein the die interconnects include a plurality of pins coupled to the semiconductor die, wherein the plurality of pins facilitate the electrical communication between the first plurality of routing traces and the semiconductor die.

8. A method for manufacturing an electronic device, comprising:
fully enclosing a semiconductor die in a first molding material;
forming a first routing layer having a first routing layer footprint, wherein the first routing layer includes a first plurality of routing traces and the first plurality of routing traces are in electrical communication with die interconnects of the semiconductor die;
encapsulating the first routing layer and the first molding material in a second molding material;
forming a second routing layer having a second routing layer footprint, wherein the second routing layer is coupled to the first routing layer and the second routing layer footprint is greater than the first routing layer footprint.

9. The method of claim 8 , further comprising forming a second molding material such that the second molding material encloses a first portion of the semiconductor die.

10. The method of claim 9 , further comprising encapsulating a portion of the second molding material with the first molding material.

11. The method of claim 9 , further comprising forming the second molding material such that the second molding material forms a direct interface with a portion of the first routing layer.

12. The method of claim 9 , further comprising removing a second portion of the semiconductor die and a portion of the second molding material such that a surface of the semiconductor die is exposed.

13. The method of claim 12 , wherein the second portion of the semiconductor die is removed simultaneously with the second molding material.

14. The method of claim 9 , wherein the first plurality of routing traces are substantially coextensive with the second molding material.

15. The method of claim 8 , wherein the second plurality of routing traces are substantially coextensive with the first molding material.

16. The method of claim 8 , further comprising removing a second portion the semiconductor die and the first molding material such that a surface of the semiconductor die is exposed.

17. The method of claim 16 , wherein the second portion of the semiconductor die is removed simultaneously with the first molding material.

18. An electronic device, comprising:
a semiconductor die having a first surface and a second surface, wherein the second surface includes die interconnects;
a first routing layer coupled to the die interconnects of the semiconductor die, the first routing layer including:
a first substrate,
a first plurality of routing traces in electrical communication with the semiconductor die, wherein the first plurality of routing traces are positioned within a first routing footprint and the first routing footprint has a width greater than a width of the semiconductor die;

a second routing layer coupled to the first routing layer, the second routing layer including:
a second substrate,
a second plurality of routing traces in electrical communication with the first plurality of routing traces, wherein the second plurality of routing traces are positioned within a second routing footprint, and
wherein the second routing footprint has a width greater than the width of the first routing footprint;
a first molding material forming a direct interface with the first substrate and fully enclosing the semiconductor die; and
a second molding material forming a direct interface with the first molding material and the second substrate.

19. The electronic device of claim 18 , wherein the first substrate is molded over the first plurality of routing traces.

20. The electronic device of claim 18 , further comprising a third routing layer, including:
a third substrate, and
a third plurality of wiring traces in electrical communication with either the first plurality of routing traces or the second plurality of routing traces.

Assignees

• Intel Ip Corp

Inventors

• Keser Lizabeth
• Ort Thomas
• Wagner Thomas
• Waidhas Bernd

Classifications

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W70/655

  Fan-out layouts · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W70/6528

  of the portions that connect to chips, wafers or package parts · CPC title

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title