Thermally enhanced semiconductor assembly with three dimensional integration and method of making the same

Patent metadata

Field	Value
Publication number	US-2017194300-A1
Application number	US-201715462536-A
Country	US
Kind code	A1
Filing date	Mar 17, 2017
Priority date	May 27, 2015
Publication date	Jul 6, 2017
Grant date	—

Abstract

A thermally enhanced semiconductor assembly with three dimensional integration includes a first component and a second component face-to-face mounted together. A heat spreader that provides an enhanced thermal characteristic for the semiconductor assembly is disposed in a through opening of a routing circuitry. Another routing circuitry disposed on the heat spreader not only provides mechanical support, but also allows heat spreading and electrical grounding for the heat spreader by metallized vias.

First claim

What is claimed is:

1 . A thermally enhanced semiconductor assembly with three dimensional integration, comprising:
a first component that includes a first device and a buildup circuitry, wherein the first device is electrically coupled to a first surface of the buildup circuitry; a second component that includes a second device, a first routing circuitry, a second routing circuitry and a heat spreader, wherein (i) the first routing circuitry has a first surface, an opposite second surface, and a through opening extending from the first surface to the second surface, (ii) the heat spreader is disposed in the through opening and has a backside surface substantially coplanar with the second surface of the first routing circuitry, (iii) the second routing circuitry is disposed on the backside surface of the heat spreader and the second surface of the first routing circuitry and electrically connected to the first routing circuitry and thermally conductible to the heat spreader through metallized vias, and (iv) the second device is attached to the heat spreader with a thermally conductive material and laterally surrounded by the first routing circuitry; and the first component is stacked over the second component, with the second device electrically coupled to a second surface of the buildup circuitry opposite to the first surface by an array of first bumps, and with the second surface of the buildup circuitry electrically coupled to the first surface of the first routing circuitry by an array of second bumps.

2 . The semiconductor assembly of claim 1 , further comprising a metal layer that is integrally formed with the heat spreader and disposed on sidewalls of the through opening

3 . The semiconductor assembly of claim 1 , wherein the first routing circuitry includes at least one conductive trace laterally extending beyond peripheral edges of the first component.

4 . The semiconductor assembly of claim 3 , further comprising a third device stacked over the first component and electrically coupled to the first surface of the first routing circuitry.

5 . The semiconductor assembly of claim 3 , further comprising a wiring board stacked over the first component, the wiring board including a third routing circuitry, a fourth routing circuitry and an additional heat spreader, wherein (i) the third routing circuitry has a first surface, an opposite second surface, and a through opening extending from the first surface to the second surface, (ii) the additional heat spreader is disposed in the through opening and has a backside surface substantially coplanar with the first surface of the third routing circuitry, (iii) the fourth routing circuitry is disposed on the backside surface of the additional heat spreader and the first surface of the third routing circuitry and electrically connected to the third routing circuitry and thermally conductible to the additional heat spreader through metallized vias, and (iv) the first component is attached to the additional heat spreader and laterally surrounded by the third routing circuitry.

6 . The semiconductor assembly of claim 5 , further comprising a third device stacked over and electrically coupled to the fourth routing circuitry.

7 . The semiconductor assembly of claim 3 , further comprising another heat spreader electrically coupled to the first surface of the first routing circuitry and thermally conductible to the first device of the first component.

8 . The semiconductor assembly of claim 1 , wherein the first component further includes a molding compound that surrounds the first device and covers the first surface of the buildup circuitry.

9 . The semiconductor assembly of claim 8 , wherein the first component further includes an array of vertical connecting elements in the molding compound that are electrically coupled to the buildup circuitry and extend towards an exterior surface of the molding compound.

10 . The semiconductor assembly of claim 9 , further comprising a third device stacked over the first component and electrically coupled to the vertical connecting elements of the first component.

11 . The semiconductor assembly of claim 9 , wherein the first component further includes an external routing circuitry disposed on the exterior surface of the molding compound and electrically coupled to the vertical connecting elements in the molding compound.

12 . A method of making a thermally enhanced semiconductor assembly with three dimensional integration, comprising:
providing a first component that includes a first device and a buildup circuitry, wherein the first device is electrically coupled to a first surface of the buildup circuitry; providing a wiring board that includes a first routing circuitry, a second routing circuitry and a heat spreader, wherein (i) the first routing circuitry has a first surface, an opposite second surface, and a through opening extending from the first surface to the second surface, (ii) the heat spreader is disposed in the through opening and has a backside surface substantially coplanar with the second surface of the first routing circuitry, and (iii) the second routing circuitry is disposed on the backside surface of the heat spreader and the second surface of the first routing circuitry and electrically connected to the first routing circuitry and thermally conductible to the heat spreader through metallized vias; electrically coupling a second device to a second surface of the buildup circuitry of the first component opposite to the first surface through an array of first bumps; and stacking the first component over the wiring board and electrically coupling the first surface of the first routing circuitry to the second surface of the buildup circuitry of the first component by an array of second bumps, with the second device attached to the heat spreader and laterally surrounded by the first routing circuitry.

13 . The method of claim 12 , further comprising a step of stacking a third device over the first component, wherein the third device is electrically coupled to the first surface of the first routing circuitry.

14 . The method of claim 12 , further comprising steps of:
providing an additional wiring board that includes a third routing circuitry, a fourth routing circuitry and an additional heat spreader, wherein (i) the third routing circuitry has a first surface, an opposite second surface, and a through opening extending from the first surface and the second surface, (ii) the additional heat spreader is disposed in the through opening and has a backside surface substantially coplanar with the first surface of the third routing circuitry, and (iii) the fourth routing circuitry is disposed on the backside surface of the additional heat spreader and the first surface of the third routing circuitry and electrically connected to the third routing circuitry and thermally conductible to the additional heat spreader through metallized vias; and stacking the additional wiring board over the first component, with the second surface of the third routing circuitry electrically coupled to the first surface of the first routing circuitry, and with the first component attached to the additional heat spreader and laterally surrounded by the third routing circuitry.

15 . The method of claim 14 , further comprising a step of stacking a third device over the fourth routing circuitry, wherein the third device is electrically coupled to the fourth routing circuitry.

16 . The method of claim 12 , further comprising a step of stacking an additional heat spreader over the first component, wherein the addi

Assignees

• Bridge Semiconductor Corp

Inventors

• Lin Charles W C
• Wang Chia-Chung

Classifications

• H10W70/682

  comprising holes having chips therein · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title

• H10W90/22

  the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title