Device structure having inter-digitated back to back MOSFETs

Patent metadata

Field	Value
Publication number	US-10388781-B2
Application number	US-201615161054-A
Country	US
Kind code	B2
Filing date	May 20, 2016
Priority date	May 20, 2016
Publication date	Aug 20, 2019
Grant date	Aug 20, 2019

Abstract

A bi-directional switch device includes two inter-digitated back-to-back vertical metal oxide semiconductor field effect transistors (MOSFETs) formed on a substrate with their drains connected together, but otherwise isolated from each other.

First claim

What is claimed is:

1. A bi-directional switch device, comprising:
a semiconducting substrate;
two inter-digitated back-to-back vertical metal oxide semiconductor field effect transistors (MOSFETs) formed on the substrate, with their drains connected together, but otherwise isolated from each other, wherein each of the two inter-digitated back-to-back vertical MOSFETs has a number of active cells with one or more active gate trenches, wherein a pitch of a plurality of segments corresponding to two inter-digitated back-to-back vertical MOSFETs is selected such that a source-to-source current path between the two inter-digitated back-to-back MOSFETs is predominantly lateral current flow in a drift region of the two MOSFETs; and
a termination structure formed between the two MOSFETs having one or more trenches, each in a size different from that of each of one or more active gate trenches in the active cells in the two MOSFETs.

2. The device of claim 1 , wherein the two inter-digitated back-to-back vertical MOSFETs include a first vertical MOSFET having a plurality of segments, and a second vertical MOSFET having one or more segments, wherein the one or more segments of the second vertical MOSFET includes a segment disposed between two segments of the plurality of segments of the first vertical MOSFET.

3. The device of claim 2 , wherein a pitch of the plurality of segments of the first vertical MOSFET is between 10 μm and 100 μm.

4. The device of claim 2 , wherein a thickness of the semiconducting substrate is greater than 75 microns.

5. The device of claim 2 , wherein a thickness of the semiconducting substrate is between 3 mils and 6 mils.

6. The device of claim 2 , wherein a width of each segment of the plurality of segments in the first and second MOSFETs is between 500 μm and 5 mm.

7. The device of claim 2 , wherein each segment of the first and second MOSFETs has between 10 and 200 active cells.

8. The device of claim 1 , further comprising an electrically isolated metal layer formed on the substrate, wherein gate and source regions of the two inter-digitated back-to-back MOSFETs are electrically connected to corresponding isolated portions of the metal layer.

9. The device of claim 1 , further comprising an electrically isolated metal layer formed on the substrate, wherein source regions of the two inter-digitated back-to-back MOSFETs are electrically connected to corresponding isolated and inter-digitated portions of the metal layer.

10. The device of claim 9 , wherein gate regions of the two inter-digitated back-to-back MOSFETs are electrically connected to separate corresponding isolated gate pad portions of the metal layer.

11. The device of claim 1 , further comprising a first electrically isolated metal layer formed on the substrate and a second electrically isolated metal layer formed on a layer of insulating material sandwiched between the first metal layer and the second metal layer, wherein source regions of the two inter-digitated back-to-back MOSFETs are electrically connected to corresponding isolated and inter-digitated portions of the first metal layer and the corresponding isolated and inter-digitated portions of the first metal layer are electrically connected to corresponding electrically isolated portions of the second metal layer by conductive vias formed through the layer of an insulating material sandwiched between the first metal layer and the second metal layer.

12. The device of claim 11 , wherein gate regions of the two inter-digitated back-to-back MOSFETs are electrically connected to corresponding isolated gate portions of the first metal layer and the corresponding isolated gate portions of the first metal layer are electrically connected to corresponding electrically isolated gate pad portions of the second metal layer by conductive vias formed through the layer of insulating material sandwiched between the first metal layer and the second metal layer.

13. The device of claim 1 , wherein the one or more trenches in the termination structure extend deeper in depth than the active gate trenches and are lined with an insulating material thicker than that for the active gate trenches.

14. The device of claim 13 , wherein the termination structure includes a single trench filled with an insulator material.

15. The device of claim 1 , wherein the one or more trenches in the termination structure are shallower in depth than the active gate trenches and is only filled with an insulating material.

16. The device of claim 1 , wherein the one or more trenches in the termination structure is a single trench which extends deeper in depth than the active gate trenches and is lined with an insulating material thicker than that for the active gate trenches.

17. The device of claim 1 , further comprising a channel stop formed around the first and second inter-digitated MOSFETs.

18. The device of claim 1 , wherein a backside of the substrate has no metal layer formed on it.

19. A bi-directional switch device, comprising:
a semiconducting substrate;
a first vertical metal oxide semiconductor field effect transistor (MOSFET) formed on the substrate, the first vertical metal oxide semiconductor field effect transistor having a first source region, a first gate region disposed on a first top portion of the substrate and a first drain disposed on a first bottom portion of the substrate, a first source metal electrically connected to the first source region;
a second vertical MOSFET formed on the substrate, the second vertical metal oxide semiconductor field effect transistor comprises a second source region, a second gate region disposed on a second top portion of the substrate and a second drain disposed on a second bottom portion of the substrate, a second source metal electrically connected to the second source region, wherein each of the first and second vertical MOSFETs has a number of active cells with one or more active gate trenches; and
an isolation structure comprising at least a trench between the first and second MOSFETs, wherein each of the at least a trench is in a size different from that of each of one or more active gate trenches in the active cells in the first and second MOSFETs, wherein the first and second drains are electrically connected together, the first source and the first gate are electrically isolated from the second source and the second gate respectively thus forming two back-to-back MOSFETs, wherein a source-to-source current path between the two back-to-back MOSFETs is predominantly lateral current flow in a drift region of the two MOSFETs.

20. The device of claim 19 , wherein a separation between the two MOSFETs is 5 micron or less.

Assignees

• Alpha & Omega Semiconductor

Inventors

• Bobde Madhur
• Lui Sik
• Pan Ji

Classifications

• H10D84/837

  comprising vertical IGFETs · CPC title

• H10W72/926

  Multiple bond pads having different sizes · CPC title

• H10D84/0151

  Manufacturing their isolation regions · CPC title

• H10D30/668 Primary

  having trench gate electrodes, e.g. UMOS transistors · CPC title

• H01L21/823487

  Electricity · mapped topic