Power MOSFET device structure for high frequency applications

Patent metadata

Field	Value
Publication number	US-8963233-B2
Application number	US-201213436192-A
Country	US
Kind code	B2
Filing date	Mar 30, 2012
Priority date	May 9, 2005
Publication date	Feb 24, 2015
Grant date	Feb 24, 2015

Abstract

This invention discloses a new switching device that includes a drain disposed on a first surface and a source region disposed near a second surface of a semiconductor opposite the first surface. An insulated gate electrode is disposed on top of the second surface for controlling a source to drain current and a source electrode is interposed into the insulated gate electrode for substantially preventing a coupling of an electrical field between the gate electrode and an epitaxial region underneath the insulated gate electrode. The source electrode further covers and extends over the insulated gate for covering an area on the second surface of the semiconductor to contact the source region, An epitaxial layer is disposed above and having a different dopant concentration than the drain region. The gate electrode is insulated from the source electrode by an insulation layer having a thickness depending on a Vgsmax rating of the vertical power device.

First claim

We claim:

1. A switching device supported on a semiconductor comprising a drain disposed on a first surface and a source region disposed near a second surface of said semiconductor opposite said first surface, wherein said switching device further comprising:
an insulated gate electrode disposed on top of said second surface for controlling a source to drain current wherein the gate electrode comprising a first gate segment and a second gate segment wherein the first and second gate segments disposed substantially parallel to the second surface of the semiconductor substrate and having a disconnected gap between the first gate and the second gate segment; and
a dielectric layer covering over first and second gate segments and filling a lower part of the disconnected gap with a source electrode layer covering over the dielectric layer having an interposing portion filling an upper part of the gap between the first and second gate segments.

2. The switching device of claim 1 wherein:
said source electrode layer further covering and extending over said dielectric layer for covering an area on said second surface of said semiconductor on top of and in contact with said source region.

3. The switching device of claim 1 wherein:
said semiconductor substrate further includes an epitaxial layer disposed above and having a different dopant concentration than said drain region.

4. The switching device of claim 1 wherein:
said dielectric layer having a thickness in compliance with a Vgsmax rating of said vertical power device.

5. The switching device of claim 1 wherein:
said dielectric layer having a greater thickness surrounding outer edges of said gate electrode opposite the disconnected gap between the first and second gate segments.

6. The switching device of claim 1 wherein:
said switching device further comprising a N-channel MOSFET cell.

7. The switching device of claim 1 wherein:
said switching device further comprising a P-channel MOSFET cell.

Assignees

• Bhalla Anup
• Ng Daniel
• Li Tiesheng
• Lui Sik K
• Alpha & Omega Semiconductor

Inventors

• Bhalla Anup
• Ng Daniel
• Li Tiesheng
• Lui Sik K

Classifications

• H10D64/2527

  for vertical devices wherein the source or drain electrodes are recessed in semiconductor bodies · CPC title

• H10D30/662

  having a drift region having a doping concentration that is higher between adjacent body regions relative to other parts of the drift region · CPC title

• H10D62/393

  Body regions of DMOS transistors or IGBTs  (cell layout of DMOS H10D62/127) · CPC title

• H10D62/157

  Impurity concentrations or distributions · CPC title

• H10D64/518

  characterised by their lengths or sectional shapes · CPC title