Semiconductor device

Patent metadata

Field	Value
Publication number	US-9825024-B2
Application number	US-201514870141-A
Country	US
Kind code	B2
Filing date	Sep 30, 2015
Priority date	Sep 30, 2015
Publication date	Nov 21, 2017
Grant date	Nov 21, 2017

Abstract

A semiconductor device is provided. The semiconductor device includes an active region, a gate line, a first metal interconnect, a power rail, and a second metal interconnect. The gate line overlaps the active region and extends along a first direction. The first metal interconnect overlaps the active region and the gate line. The first metal interconnect extends along a second direction intersecting the first direction. The power rail is disposed in a higher layer than the first metal interconnect. The power rail extends along the second direction. The second metal interconnect is disposed in a same layer as the power rail, the second metal interconnect extends along the second direction.

First claim

What is claimed is:

1. A semiconductor device comprising:
an active region;
a gate line which overlaps the active region and extends along a first direction;
a first metal interconnect which overlaps the active region and the gate line, the first metal interconnect extending along a second direction intersecting the first direction, wherein a first surface of the first metal interconnect directly contacts a first surface of the gate line such that a layer or an element is not disposed between the first surface of the first metal interconnect and the first surface of the gate line;
a power rail disposed in a higher layer than the first metal interconnect, the power rail extending along the second direction; and
a second metal interconnect disposed in a same layer as the power rail, the second metal interconnect extending along the second direction.

2. The semiconductor device of claim 1 , wherein the gate line is disposed in a first layer, the first metal interconnect is disposed in a second layer, and the second metal interconnect is disposed in a third layer,
wherein the second layer is disposed on the first layer, and the third layer is disposed on the second layer.

3. The semiconductor device of claim 1 , wherein the power rail overlaps an end of the gate line.

4. The semiconductor device of claim 1 , wherein a first distance between the second metal interconnect and the power rail in the first direction is smaller than a second distance between the first metal interconnect and the power rail in the first direction.

5. The semiconductor device of claim 4 , wherein the first metal interconnect comprises a plurality of metal interconnects, wherein the plurality of metal interconnects are separated from the power rail in the first direction by a distance greater than the first distance.

6. The semiconductor device of claim 1 , wherein the active region comprises a first active region and a second active region separated from the first active region in the first direction, and a gate pickup region is disposed between the first active region and the second active region.

7. The semiconductor device of claim 6 , wherein the gate line comprises a first gate part which overlaps the first active region, a second gate part which overlaps the gate pickup region, and a third gate part which overlaps the second active region.

8. The semiconductor device of claim 7 , wherein the first metal interconnect comprises a plurality of metal interconnects,
wherein at least one of the plurality of metal interconnects overlaps the second gate part.

9. The semiconductor device of claim 1 , further comprising a fast contact formed on the active region,
wherein the first contact overlaps the second metal interconnect,
wherein the first contact is disposed in a lower layer than the second metal interconnect.

10. The semiconductor device of claim 9 , further comprising a second contact formed on the gate line,
wherein the second contact is disposed in a lower layer than the second metal interconnect.

11. The semiconductor device of claim 10 , wherein the first contact and the second contact are disposed in a same layer as each other.

12. A semiconductor device comprising:
a first layer including an active region;
a gate line formed in the first layer;
a second layer disposed on the first layer;
a first metal interconnect formed in the second layer, the first metal interconnect overlapping the active region, wherein a first surface of the first metal interconnect directly contacts a first surface of the gate line such that a layer or an element is not disposed between the first surface of the first metal interconnect and the first surface of the gate line;
a third layer disposed on the second layer;
a second metal interconnect formed in the third layer, wherein the second metal interconnect overlaps the active region, and the second metal interconnect does not overlap the first metal interconnect; and
a power rail formed in the third layer, wherein the power rail does not overlap the active region, and the power rail is electrically connected to the second metal interconnect to supply power to the second metal interconnect,
wherein an upper surface of the first metal interconnect lies in a same plane as a lower surface of the second metal interconnect and a lower surface of the power rail.

13. The semiconductor device of claim 12 , further comprising a first contact formed on the active region and a second contact formed on the gate line.

14. The semiconductor device of claim 13 , wherein the first and second contacts are formed in the second layer.

15. The semiconductor device of claim 12 , wherein a first distance between the second metal interconnect and the power rail is smaller than a second distance between the first metal interconnect and the power rail.

16. The semiconductor device of claim 1 , wherein an upper surface of the first metal interconnect lies in a same plane as a lower surface of the second metal interconnect and a lower surface of the power rail.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jung Jong-Hoon

Classifications

• H10W20/427 Primary

  Power or ground buses · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H01L27/10897

  Electricity · mapped topic

• H01L29/78

  Electricity · mapped topic

• H01L27/0292 Primary

  Electricity · mapped topic