Integrated circuit package structure and testing method using the same

Patent metadata

Field	Value
Publication number	US-10347548-B2
Application number	US-201715438894-A
Country	US
Kind code	B2
Filing date	Feb 22, 2017
Priority date	Dec 6, 2016
Publication date	Jul 9, 2019
Grant date	Jul 9, 2019

Abstract

An integrated circuit package structure includes a device die having a plurality of metal pillars, a molding material directly in contact with at least one side surface of the device die, a first dielectric layer disposed on the device die and on the molding material, and a testing pad disposed in the first dielectric layer and directly in contact with an interface between the device die and the molding material. The testing pad is electrical isolated from the metal pillars.

First claim

What is claimed is:

1. An integrated circuit package structure, comprising:
a device die comprising a plurality of metal pillars;
a molding material directly in contact with at least one side surface of the device die;
a first dielectric layer disposed on the device die and on the molding material; and
a testing pad disposed in the first dielectric layer and directly in contact with an interface between the device die and the molding material, wherein the testing pad is electrical isolated from the metal pillars.

2. The integrated circuit package structure of claim 1 , further comprising:
at least one second dielectric layer disposed on the testing pad and on the first dielectric layer; and
two vias disposed in the second dielectric layer, wherein the vias are connected to two opposite ends of the testing pad, respectively.

3. The integrated circuit package structure of claim 1 , further comprising:
a plurality of redistribution lines disposed above the first dielectric layer, wherein the redistribution lines are respectively connected to the metal pillars of the device die, and the redistribution lines and the interface are spaced by the first dielectric layer.

4. The integrated circuit package structure of claim 3 , further comprising:
at least one second dielectric layer disposed on the first dielectric layer, wherein the redistribution lines are disposed in the second dielectric layer and are electrical isolated from the testing pad.

5. The integrated circuit package structure of claim 4 , further comprising:
a plurality of electrical connectors disposed on the second dielectric layer and connected to at least some of the redistribution lines.

6. The integrated circuit package structure of claim 3 , further comprising a plurality of though-vias disposed in the molding material, wherein the through-vias are connected to at least some of the redistribution lines, respectively.

7. The integrated circuit package structure of claim 6 , further comprising a plurality of solder regions connected to the through-vias.

8. The integrated circuit package structure of claim 6 , wherein the redistribution lines interconnect the through-vias and the metal pillars, respectively.

9. The integrated circuit package structure of claim 6 , wherein the testing pad is electrical isolated from the through-vias.

10. The integrated circuit package structure of claim 1 , wherein the testing pad is a serpentine pattern.

11. An integrated circuit package structure, comprising:
a device die comprising a plurality of metal pillars;
a molding material directly in contact with at least one side surface of the device die;
a plurality of through-vias disposed in the molding material;
a plurality of redistribution lines interconnecting the metal pillars and the through-vias, respectively; and
a testing pad disposed directly in contact with an interface between the device die and the molding material, wherein the testing pad is electrical isolated from the redistribution lines.

12. The integrated circuit package structure of claim 11 , wherein the testing pad comprises:
a plurality of first sections, wherein two opposite ends of the each of the first sections are respectively disposed on the device die and on the molding material; and
a plurality of second sections configured to connect the first sections.

13. The integrated circuit package structure of claim 12 , wherein the first sections and the second sections are serially connected.

14. The integrated circuit package structure of claim 12 , wherein a major axis of each of the first sections is substantially perpendicular to the interface.

15. The integrated circuit package structure of claim 11 , wherein the testing pad and the redistribution lines are at different levels.

16. The integrated circuit package structure of claim 11 , wherein the testing pad and the metal pillars are electrical isolated.

17. The integrated circuit package structure of claim 11 , wherein the testing pad and the through-vias are electrical isolated.

18. The integrated circuit package structure of claim 11 , wherein the testing pad is a serpentine metal line.

19. An integrated circuit package structure, comprising:
a device die comprising a metal pillar;
a molding material adjacent to a side surface of the device die;
a redistribution line directly in contact the metal pillar; and
a testing pad directly in contact with a top surface of the device die and a top surface of the molding material and electrical isolated from the redistribution line.

20. The integrated circuit package structure of claim 19 , wherein the testing pad is in contact with an interface between the device die and the molding material.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Yang-Che
• Chou Tsung-Te
• Lin Chen-Hua
• Tseng Huang-Wen
• Liu Chwen-Ming

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W70/099

  Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers · CPC title

• H10W72/877

  Bump connectors and die-attach connectors · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title