Semiconductor chips with seal rings and electronic test structures, semiconductor wafers including the semiconductor chips, and methods for fabricating the same

Patent metadata

Field	Value
Publication number	US-9728474-B1
Application number	US-201615278257-A
Country	US
Kind code	B1
Filing date	Sep 28, 2016
Priority date	Sep 28, 2016
Publication date	Aug 8, 2017
Grant date	Aug 8, 2017

Abstract

A semiconductor chip includes an active area including a plurality of integrated circuit structures, a seal ring enclosing the active area, a corner area of the semiconductor chip that is outside of the seal ring, and an electronic test structure disposed within the corner area. Semiconductor wafers including the above-noted semiconductor chips, as well as methods for fabricating semiconductor wafers including the above-noted semiconductor chips, are also disclosed.

First claim

What is claimed is:

1. A semiconductor chip comprising:
an active area including a plurality of integrated circuit structures;
a seal ring enclosing the active area;
a corner area of the semiconductor chip that is outside of the seal ring; and
an electronic test structure disposed within the corner area, wherein the electronic test structure comprises a magnetic tunnel junction (MTJ) in between bottom and top electrode layers connected by vias, and disposed within an insulating dielectric layer.

2. The semiconductor chip of claim 1 , wherein the active area comprises a semiconductor material, and wherein the plurality of integrated circuit structures are selected from the group consisting of: transistors, diffusions, memory arrays and interconnections.

3. The semiconductor chip of claim 1 , wherein the seal ring comprises a single-walled structure.

4. The semiconductor chip of claim 1 , wherein the seal ring comprises a dual-walled structure, wherein a concentric inner wall of the seal ring has a thickness that is less than a thickness of a concentric outer wall of the seal ring.

5. The semiconductor chip of claim 1 , wherein the seal ring comprises stacked conductive layers and via layers disposed through dielectric layers.

6. The semiconductor chip of claim 1 , wherein the semiconductor chip is configured in a substantial rectangular form, and wherein the seal ring is provided in a substantially octagonal form, thereby forming four corner areas of the semiconductor chip outside of the seal ring, each of the four corner areas comprising an electronic test structure.

7. The semiconductor chip of claim 1 , wherein the electronic test structure is provided in a contactless configuration that excludes contact pads.

8. The semiconductor chip of claim 1 , wherein the electronic test structure comprises a contact pad connected thereto, the contact pad being formed outside of the corner area and outside of the active area.

9. A semiconductor wafer comprising a plurality of semiconductor chips, wherein each semiconductor chip is separated from another semiconductor chip by a plurality of scribe lines configured to allow for singulation of the semiconductor wafer, wherein each semiconductor chip comprises:
an active area including a plurality of integrated circuit structures;
a seal ring enclosing the active area;
a corner area of the semiconductor chip that is outside of the seal ring; and
an electronic test structure disposed within the corner area, wherein the electronic test structure comprises a magnetic tunnel junction (MTJ) in between bottom and top electrode layers connected by vias, and disposed within an insulating dielectric layer.

10. The semiconductor wafer of claim 9 , wherein the active area comprises a semiconductor material, and wherein the plurality of integrated circuit structures are selected from the group consisting of: transistors, diffusions, memory arrays and interconnections.

11. The semiconductor wafer of claim 9 , wherein the seal ring comprises a single-walled structure.

12. The semiconductor wafer of claim 9 , wherein the seal ring comprises a dual-walled structure, wherein a concentric inner wall of the seal ring has a thickness that is less than a thickness of a concentric outer wall of the seal ring.

13. The semiconductor wafer of claim 9 , wherein the seal ring comprises stacked conductive layers and via layers disposed through dielectric layers.

14. The semiconductor wafer of claim 9 , wherein the semiconductor chip is configured in a substantial rectangular form, and wherein the seal ring is provided in a substantially octagonal form, thereby forming four corner areas of the semiconductor chip outside of the seal ring, each of the four corner areas comprising an electronic test structure.

15. The semiconductor wafer of claim 9 , wherein the electronic test structure is provided in a contactless configuration that excludes contact pads.

16. The semiconductor wafer of claim 9 , wherein the electronic test structure comprises a contact pad connected thereto, the contact pad being formed outside of the corner area and outside of the active area.

Assignees

• Globalfoundries Sg Pte Ltd

Inventors

• Yi Wanbing
• Tan Juan Boon
• Bhatkar Mahesh
• Shum Danny Pak-Chum

Classifications

• H10W76/60

  Seals · CPC title

• H10W74/137

  the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence) · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W42/00

  Arrangements for protection of devices (arrangements for thermal protection H10W40/00) · CPC title

• H10P74/273 Primary

  Interconnections for measuring or testing, e.g. probe pads · CPC title