Fan-out semiconductor package

Patent metadata

Field	Value
Publication number	US-10332843-B2
Application number	US-201715667315-A
Country	US
Kind code	B2
Filing date	Aug 2, 2017
Priority date	Aug 19, 2016
Publication date	Jun 25, 2019
Grant date	Jun 25, 2019

Abstract

A fan-out semiconductor package includes a semiconductor chip disposed in a through-hole of a first connection member having the through-hole and a second connection member disposed on an active surface of the semiconductor chip. A plurality of dummy vias surrounding the semiconductor chip are disposed in the first connection member.

First claim

What is claimed is:

1. A fan-out semiconductor package, comprising:
a first connection member having a through-hole;
a semiconductor chip disposed in the through-hole of the first connection member and having an active surface with connection pads disposed thereon and an inactive surface opposite the active surface;
an encapsulant encapsulating at least a portion of the first connection member and the inactive surface of the semiconductor chip; and
a second connection member disposed on the first connection member and the active surface of the semiconductor chip, wherein
the first connection member and the second connection member include, respectively, redistribution layers electrically connected to the connection pads of the semiconductor chip,
the redistribution layer of the first connection member includes a signal pattern and a ground pattern, and
the first connection member includes a plurality of dummy vias connected to the ground pattern and surrounding the semiconductor chip.

2. The fan-out semiconductor package of claim 1 , further comprising a metal layer disposed on the encapsulant and covering at least a portion of the inactive surface of the semiconductor chip,
wherein the metal layer is connected to the plurality of dummy vias.

3. The fan-out semiconductor package of claim 1 , wherein the first connection member includes a plurality of signal vias connected to the signal pattern.

4. The fan-out semiconductor package of claim 3 , wherein the plurality of dummy vias are disposed along an outer edge of the first connection member and surround the plurality of signal vias.

5. The fan-out semiconductor package of claim 3 , wherein the plurality of dummy vias are disposed along an inner edge of the first connection member and are surrounded by the plurality of signal vias.

6. The fan-out semiconductor package of claim 1 , wherein the plurality of dummy vias are spaced apart from each other by a predetermined interval.

7. The fan-out semiconductor package of claim 6 , wherein the plurality of dummy vias are connected to each other by a plurality of line vias.

8. The fan-out semiconductor package of claim 1 , wherein the plurality of dummy vias overlap each other.

9. The fan-out semiconductor package of claim 3 , further comprising a memory package disposed on the encapsulant and electrically connected to the plurality of signal vias.

10. The fan-out semiconductor package of claim 1 , wherein the first connection member includes a first insulating layer, a first redistribution layer in contact with the second connection member and embedded in the first insulating layer, and a second redistribution layer disposed on a surface of the first insulating layer opposite a surface of the first insulating layer having the first redistribution layer embedded therein, and
the plurality of dummy vias include first dummy vias penetrating through the first insulating layer.

11. The fan-out semiconductor package of claim 10 , wherein the first connection member further includes a second insulating layer disposed on the first insulating layer and covering the second redistribution layer and a third redistribution layer disposed on the second insulating layer, and
the plurality of dummy vias further include second dummy vias penetrating through the second insulating layer.

12. The fan-out semiconductor package of claim 10 , wherein a distance between the redistribution layer of the second connection member and the first redistribution layer is greater than a distance between the redistribution layer of the second connection member and the connection pad of the semiconductor chip.

13. The fan-out semiconductor package of claim 1 , wherein the first connection member includes a first insulating layer, a first redistribution layer and a second redistribution layer disposed on opposite surfaces of the first insulating layer, a second insulating layer disposed on the first insulating layer and covering the first redistribution layer, and a third redistribution layer disposed on the second insulating layer, and
the plurality of dummy vias include first and second dummy vias respectively penetrating through the first and second insulating layers.

14. The fan-out semiconductor package of claim 13 , wherein the first connection member further includes a third insulating layer disposed on the first insulating layer and covering the second redistribution layer and a fourth redistribution layer disposed on the third insulating layer, and
the plurality of dummy vias include first, second, and third dummy vias respectively penetrating through the first, second, and third insulating layers.

15. The fan-out semiconductor package of claim 13 , wherein a thickness of the first insulating layer is greater than a thickness of the second insulating layer.

16. A fan-out semiconductor package, comprising:
a first connection member having a through-hole;
a semiconductor chip disposed in the through-hole of the first connection member and having an active surface with connection pads disposed thereon and an inactive surface opposite the active surface; and
a second connection member disposed on the first connection member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads of the semiconductor chip, wherein
the first connection member includes a plurality of signal vias and a plurality of dummy vias, and
the plurality of dummy vias surround the plurality of signal vias or are surrounded by the plurality of signal vias.

17. A fan-out semiconductor package, comprising:
a first connection member having a through-hole;
a semiconductor chip disposed in the through-hole of the first connection member and having an active surface with connection pads disposed thereon and an inactive surface opposite the active surface;
an encapsulant encapsulating at least a portion of the first connection member and the inactive surface of the semiconductor chip; and
a second connection member disposed on the first connection member and the active surface of the semiconductor chip, wherein
the first connection member and the second connection member include, respectively, redistribution layers electrically connected to the connection pads of the semiconductor chip,
the redistribution layer of the first connection member includes a signal pattern and a ground pattern,
the first connection member includes a plurality of signal vias and a plurality of dummy vias, the plurality of dummy vias being connected to the ground pattern and surrounding the semiconductor chip, and
the plurality of dummy vias and the plurality of signal vias are radially offset from each other.

18. The fan-out semiconductor package of claim 17 , wherein the first connection member includes a first insulating layer, a first redistribution layer and a second redistribution layer disposed on opposite surfaces of the first insulating layer, a second insulating layer disposed on the first insulating layer and covering the first redistribution layer, and a third redistribution layer disposed on the second insulating layer, and
the plurality of dummy vias include first and second dummy vias respectively penetrating through the first and second insulating layers.

19. The fan-out semiconductor package of claim 17 , wherein the first connection member includes:
a first insulating layer,
a first redistribution layer and a second redistribution layer disposed on opposite surfaces of the first insulating layer,
a second

Assignees

• Samsung Electro Mech

Inventors

• Baek Yong Ho
• Yi Moon Hee
• Lim Kyung Sang

Classifications

• H10W42/276

  the arrangements being on an external surface of the package, e.g. on the outer surface of an encapsulation · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title