Electromagnetic interference shield for semiconductor chip packages

Patent metadata

Field	Value
Publication number	US-9368455-B2
Application number	US-201414229771-A
Country	US
Kind code	B2
Filing date	Mar 28, 2014
Priority date	Mar 28, 2014
Publication date	Jun 14, 2016
Grant date	Jun 14, 2016

Abstract

An electromagnetic interference shield is described for semiconductor chip packages. In some embodiments, a package has a semiconductor die. a redistribution layer, a mold compound over the die, a plurality of vias through the mold compound and outside the die to form a shield, and a metal film over the vias. and over the mold compound.

First claim

What is claimed is:

1. A shielded semiconductor device package comprising:
a semiconductor die having a front side and a back side;
a front side redistribution layer having a ground layer;
a mold compound over the back side of the die and over the front side redistribution layer;
a plurality of vias through the mold compound and outside the die to form a shield, wherein the bottoms of the vias are over a ground layer of the front side redistribution layer; and
a single continuous metal shielding film over the back side of the mold compound and into the vias, wherein the shielding film in some of the vias directly connects to the ground layer and wherein the shielding film in some of the vias does not directly connect to the ground layer of the front side redistribution layer.

2. The package of claim 1 , wherein the ground layer is connected to external connection pads of the redistribution layer to connect to an external ground.

3. The package of claim 1 , wherein the die is rectangular having four sides and the vias extend vertically from the redistribution layer on all four sides of the die.

4. The package of claim 3 , wherein the vias are in straight rows along each of the four sides of the die.

5. The package of claim 3 , wherein the vias are further in a second straight row along each of the four sides of the die.

6. The package of claim 5 , wherein the vias of the second row alternate in position with the vias of the first row.

7. The package of claim 1 , wherein the redistribution layer is a package substrate.

8. The package of claim 1 , wherein the redistribution layer is a bumpless build-up layer.

9. The package of claim 1 , wherein the vias are filled with an electrically conductive material.

10. The package of claim 1 , wherein the metal film is titanium or copper.

11. The package of claim 1 , further comprising a panel level ball grid array to connect to a system board.

12. An apparatus comprising:
a system board;
a radio frequency die package connected to the system board; and
a shielded semiconductor device package connected to the system board, the semiconductor device package having a semiconductor die having a front side and a back side, a front side redistribution layer having a ground layer, a mold compound over the back side of the die and over the front side redistribution layer, a plurality of vias through the mold compound and outside the die to form a shield, wherein the bottoms of the vias are over a ground layer of the front side redistribution layer and a single continuous metal shielding film over the back side of the mold compound and into the vias, wherein the shielding film in some of the vias directly connects to the ground layer and wherein the shielding film in some of the vias does not directly connect to the ground layer of the front side redistribution layer.

13. The apparatus of claim 12 , wherein the vies are arranged in a row along each edge of the semiconductor die.

Assignees

• Mahajan Ravindranath V
• Guzek John S
• Elsherbini Adel A
• Deshpande Nitin Ashok
• Intel Corp

Inventors

• Mahajan Ravindranath V
• Guzek John S
• Elsherbini Adel A
• Deshpande Nitin Ashok

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/10

  characterised by their shape or disposition · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W72/241

  Dispositions, e.g. layouts · CPC title