Method for fabricating semiconductor device

Patent metadata

Field	Value
Publication number	US-10312146-B2
Application number	US-201715647031-A
Country	US
Kind code	B2
Filing date	Jul 11, 2017
Priority date	Jul 11, 2017
Publication date	Jun 4, 2019
Grant date	Jun 4, 2019

Abstract

A method for fabricating a semiconductor structure includes forming a plurality of mandrels over a substrate, wherein the substrate comprises a semiconductor substrate as a base. Then, a first dielectric layer is formed to cover on a predetermined mandrel of the mandrels. A second dielectric layer is formed over the substrate to cover the mandrels. The mandrels are removed, wherein a remaining portion of the first dielectric layer and the second dielectric layer at a sidewall of the mandrels remains on the substrate. An anisotropic etching process is performed over the substrate until a top portion of the semiconductor substrate is etched to form a plurality of fins corresponding to the remaining portion of the first dielectric layer and the second dielectric layer.

First claim

What is claimed is:

1. A method for fabricating a semiconductor structure, comprising:
forming a plurality of mandrels over a substrate, wherein the substrate comprises a semiconductor substrate as a base;
forming a first dielectric layer to cover on a predetermined mandrel of the mandrels;
forming a second dielectric layer over the substrate to cover the mandrels;
removing the mandrels, wherein a remaining portion of the first dielectric layer and the second dielectric layer at a sidewall of the mandrels remains on the substrate;
performing an anisotropic etching process over the substrate until a top portion of the semiconductor substrate is etched to form a plurality of fins corresponding to the remaining portion of the first dielectric layer and the second dielectric layer, wherein the fins comprises first fins corresponding to the first dielectric layer with the second dielectric layer and second fins corresponding to the second dielectric layer without the first dielectric layer, and the first fins are thicker than the second fins;
removing a dummy fin of the fins, wherein at least one fin of the first fins subjecting to the first dielectric layer at an area adapting for a separately isolated device remains;
depositing oxide over the substrate to form an oxide layer covering the fins as remained; and
performing an annealing process over the substrate, wherein the at least one fin of the first fins has more surface oxidation thickness due to the annealing process than the second fins.

2. The method of claim 1 , further comprising removing a top portion of the oxide layer to expose the fins.

3. The method of claim 1 , the step of forming the first dielectric layer comprises:
forming a global dielectric layer over the substrate;
forming a mask layer over the substrate to cover a predetermined sidewall of the predetermined mandrel;
removing the global dielectric layer using the mask layer as an etching mask; and
removing the mask layer.

4. The method of claim 3 , wherein the mask layer covers both the sidewall of the predetermined mandrels or just one sidewall of the predetermined mandrels.

5. The method of claim 1 , wherein the substrate further comprises a stack dielectric layer on the semiconductor substrate.

6. The method of claim 1 , wherein a thickness of the first dielectric layer is less than a thickness of the second dielectric layer.

7. The method of claim 1 , wherein a thickness of the first dielectric layer is in a range of 1-5 nm.

8. The method of claim 7 , wherein a thickness of the first dielectric layer is in a range of 1-2 nm.

9. The method of claim 7 , wherein a width of the fins is in a range of 15-20 nm.

10. The method of claim 1 , wherein a thickness of the first dielectric layer is used to compensate a semiconductor consumption on a sidewall surface of the fin corresponding to the predetermined mandrel.

11. The method of claim 1 , wherein a ratio of a thickness of the first dielectric layer to a width of the fins is in a range of 10 to 20.

12. The method of claim 1 , wherein the step of removing the mandrels comprises:
performing an etching back process on the first dielectric layer and the second dielectric layer to form a dielectric spacer on a sidewall of the mandrels, wherein the dielectric spacer of the predetermined mandrels comprises the first dielectric layer; and
removing the mandrels.

13. The method of claim 12 , wherein a material of the mandrel is a material, so to be distinct over dielectric material of the first dielectric layer and the second dielectric layer in etching.

14. The method of claim 13 , wherein a material of the mandrels is polysilicon.

15. The method of claim 13 , wherein the first dielectric layer and the second dielectric layer are silicon nitride.

16. The method of claim 1 , wherein the dummy fin as removed is abut to the at least one fin of the fins.

17. The method of claim 16 , wherein the dummy fin also comprises a fin having the first dielectric layer but not to be used.

18. The method of claim 1 , wherein the predetermined mandrel is located at an area adapting for the separately isolated device.

Assignees

• United Microelectronics Corp

Inventors

• Lin Ching-Ling
• Liang Wen-An
• Huang Chen-Ming

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10P76/405

  characterised by their composition, e.g. multilayer masks · CPC title

• H10P50/695

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• H10P14/65

  characterised by treatments performed before or after the formation of the materials · CPC title