Integrated circuit devices and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9673330-B2
Application number	US-201514965982-A
Country	US
Kind code	B2
Filing date	Dec 11, 2015
Priority date	Feb 24, 2015
Publication date	Jun 6, 2017
Grant date	Jun 6, 2017

Abstract

An integrated circuit device includes first and second fin-type active regions having different conductive type channel regions, a first device isolation layer covering both sidewalk of the first fin-type active region, and a second device isolation layer covering both sidewalls of the second fin-type active region. The first device isolation layer and the second device isolation layer have different stack structures. To manufacture the integrated circuit device, the first device isolation layer covering both sidewalls of the first fin-type active region and the second device isolation layer covering both sidewalk of the second fin-type active region are formed after the first fin-type active region and the second fin-type active region are formed. The first device isolation layer and the second device isolation layer are formed to have different stack structure.

First claim

What is claimed is:

1. An integrated circuit device comprising:
a first fin-type active region in a first region of a substrate, the first fin-type active region having a first conductive type channel region;
a first device isolation layer extending on both sidewalls of a lower portion of the first fin-type active region;
a second fin-type active region in a second region of the substrate, the second fin-type active region having a second conductive type channel region;
a second device isolation layer extending on both sidewalls of a lower portion of the second fin-type active region;
a deep trench between the first fin-type active region and the second fin-type active region, wherein a lowest level of the deep trench is below a lowest level of the first device isolation layer and the second device isolation layer; and
a third device isolation layer in the deep trench,
wherein the first device isolation layer, the second device isolation layer, and the third device isolation layer have different stack structures.

2. The integrated circuit device of claim 1 , wherein the first fin-type active region is defined by a first trench in the first region, and
wherein the first device isolation layer comprises:
a first insulating liner in contact with a sidewall of the first fin-type active region, wherein the first insulating liner is in the first trench; and
a first gapfill insulating layer in the first trench, wherein the first gapfill insulating layer is on the first insulating liner.

3. The integrated circuit device of claim 2 , wherein the second fin-type active region is defined by a second trench in the second region, and
wherein the second device isolation layer comprises:
a second insulating liner in contact with a sidewall of the second fin-type active region, wherein the second insulating liner is in the second trench;
a third insulating liner extending on the sidewall of the second fin-type active region with the second insulating liner interposed therebetween; and
a second gapfill insulating layer in the second trench, wherein the second gapfill insulating layer is on the third insulating liner.

4. An integrated circuit device comprising:
a pair of first fin-type active regions being lined up in a substantially straight line in a first region of a substrate, the pair of first fin-type active regions each having a first conductive type channel region;
a first device isolation layer extending on both sidewalls of a lower portion of each of the pair of first fin-type active regions;
a second device isolation layer extending in a direction intersecting with an extending direction of the first device isolation layer in a space between the pair of first fin-type active regions;
a pair of second fin-type active regions being lined up in a substantially straight line in a second region of the substrate, the pair of second fin-type active regions each having a second conductive type channel region;
a third device isolation layer extending on both sidewalls of a lower portion of each of the pair of second fin-type active regions; and
a fourth device isolation layer extending in a direction intersecting with an extending direction of the third device isolation layer in a space between the pair of second fin-type active regions,
wherein the first device isolation layer and the third device isolation layer have different stack structures, and the second device isolation layer and the fourth device isolation layer have different stack structures.

5. The integrated circuit device of claim 4 , wherein a first fin-type active region of the pair of first fin-type active regions is defined by a first trench in the first region, and a second fin-type active region of the pair of second fin-type active regions is defined by a second trench in the second region,
wherein the first device isolation layer comprises:
a first insulating liner in contact with the first fin-type active region; and
a first gapfill insulating layer in the first trench, wherein the first gapfill insulating layer is on the first insulating liner, and
wherein the third device isolation layer comprises:
a second insulating liner in contact with the second fin-type active region;
a third insulating liner extending on a sidewall of the second fin-type active region with the second insulating liner interposed therebetween; and
a second gapfill insulating layer in the second trench, wherein the second gapfill insulating layer is on the third insulating liner.

6. The integrated circuit device of claim 4 , wherein the second device isolation layer is in a first tin isolation region between the pair of first fin-type active regions, and the fourth device isolation layer is in a second fin isolation region between the pair of second fin-type active region,
wherein the second device isolation layer comprises;
a first insulating liner in contact with the pair of first fin-type active regions;
a first gapfill insulating layer on the first insulating liner; and
a first upper buried layer in contact with the first insulating liner and the first gapfill insulating layer, wherein the first upper buried layer is on the first gapfill insulating layer, and
wherein the fourth device isolation layer comprises;
a second insulating liner in contact with the pair of second fin-type active regions;
a third insulating liner on the second insulating liner;
a second gapfill insulating layer on the third insulating liner; and
a second upper buried layer in contact with the second insulating liner, the third insulating liner, and the second gapfill insulating layer, wherein the second upper buried layer is on the second gapfill insulating layer.

7. The integrated circuit device of claim 4 , wherein the second device isolation layer is in a first fin isolation trench between the pair of first fin-type active regions and is in a first upper trench, wherein the first upper trench has a width larger than that of the first fin isolation trench, is on the first fin isolation trench, and communicates with the first fin isolation trench, and
wherein the fourth device isolation layer is in a second fin isolation trench between the pair of second fin-type active regions and is in a second upper trench, wherein the second upper trench has a width larger than that of the second fin isolation trench, is on the second fin isolation trench, and communicates with the second fin isolation trench.

8. The integrated circuit device of claim 7 , wherein the fourth device isolation layer comprises:
a fourth oxide film in contact with the pair of second fin-type active regions, wherein the fourth oxide film is in the second fin isolation trench;
a fifth oxide film in the second fin isolation trench, wherein the fifth oxide film is on the fourth oxide film; and
an insulating liner interposed between the fourth oxide film and the fifth oxide film, wherein the insulating liner is in the second fin isolation trench and comprises a material that is different from those of the fourth and fifth oxide films; and
a sixth oxide film in contact with the fourth oxide film, the insulating liner, and the fifth oxide film, wherein the sixth oxide film is in the second upper trench.

9. The integrated circuit device of claim 8 , wherein the sixth oxide film has a width that is greater than that of the second fin isolation trench.

10. The integrated circuit device of claim 7 , wherein the second device isolation layer comprises:
a first oxide film in contact with the pair of first fin-type active regions, wherein the first oxide film is in the first fin isolation trench;
a second oxide film in the first fin isolation trench, wherein the second oxide film is on the first o

Assignees

• Chung Jae-Yup
• Lee Yoon-Seok
• Kim Hyun-Jo
• Rhee Hwa-Sung
• Jeong Hee-Don
• Park Se-Wan
• Jeong Bo-Cheol
• Samsung Electronics Co Ltd

Inventors

• Chung Jae-Yup
• Lee Yoon-Seok
• Kim Hyun-Jo
• Rhee Hwa-Sung
• Jeong Hee-Don
• Park Se-Wan
• Jeong Bo-Cheol

Classifications

• H10D30/611

  having multiple independently-addressable gate electrodes influencing the same channel (FinFETs having multiple distinct gate electrodes H10D30/6215; multi-gate TFT H10D30/6733) · CPC title

• H10D30/6215 Primary

  having multiple independently-addressable gate electrodes · CPC title

• H01L27/0924

  Electricity · mapped topic

• H01L21/823821

  Electricity · mapped topic

• H01L29/41791

  Electricity · mapped topic