Multiple finFET formation with epitaxy separation

Patent metadata

Field	Value
Publication number	US-9748245-B1
Application number	US-201615274269-A
Country	US
Kind code	B1
Filing date	Sep 23, 2016
Priority date	Sep 23, 2016
Publication date	Aug 29, 2017
Grant date	Aug 29, 2017

Abstract

A semiconductor device including an nFET device and pFET device adjacent one another. The semiconductor device includes a shallow trench isolator (STI), a gate and a substrate having fins extending upwardly through the STI. The fins include: nFET fins disposed in an nFET epi well formed in the STI and pFET fins disposed in a pFET epi well formed in the STI, a top the STI being above a top of the fins.

First claim

What is claimed is:

1. A method for forming a semiconductor device, the method comprising:
forming a plurality of fins from a substrate;
removing at least one fin to form at least a first group of fins having at least two fins and a second group of fins having at least one fin;
filling space between the fins with a shallow trench isolator (STI);
lowering a top of the STI to reveal the first and second groups of fins;
forming a nitride spacer layer over the STI and the first and second groups of fins, the nitride spacer layer having thickness equal to a fin distance between adjacent fins in the first group;
removing the nitride spacer layer that is further than the fin distance away from outer fins of the first group and an outer fin of the second group;
filling the spaces between remaining portions of the nitride spacer layer with additional STI;
removing the remaining portions of the nitride spacer layer to form first and second epi wells separated by a barrier formed by the additional STI;
forming a gate over the first and second groups of fins;
epitaxially growing source and drain contacts on either side of the gate in the first epi well; and
epitaxially growing source and drain contacts on either side of the gate in the second epi well;
wherein the barrier prevents the epitaxially grown source and drain contacts in the first epi well from contacting the epitaxially grown source and drain contacts in the second epi well.

2. The method of claim 1 , wherein forming the fins includes:
forming a fin hardmask on top of the substrate;
performing a reactive ion etching (REI) process on the substrate to remove portions of the substrate not covered by the fin hardmask.

3. The method of claim 2 , wherein removing the nitride spacer layer includes removing the fin hardmask.

4. The method of claim 1 , further comprising:
after filling the space between the fins with the shallow trench isolator (STI), performing a chemical-mechanical planarization (CMP) to level the STI and the fin hardmask.

5. The method of claim 1 , wherein a top of the epi wells is higher than a top of fins in the first or second groups.

6. The method of claim 1 , wherein the source and drains contacts in the first epi well are diamond shaped.

7. The method of claim 6 , wherein each of the fins in the first group has a diamond shaped source contact grown thereon and each of the diamond shaped contacts is in contact with an adjacent contact.

8. The method of claim 1 , wherein forming the gate includes depositing a work function metal layer on the sides of each fin in the first and second group, the metal layer having a same thickness on each side of each fin.

9. The method of claim 8 , wherein forming the gate includes depositing a work function metal layer on sides and top of each fin in the first and second group, the metal layer having a same thickness on each side of each fin.

10. A method for forming a static random access memory (SRAM) device including an nFET and a pFET adjacent to one another, the method comprising:
forming a plurality of fins from a substrate;
removing at least one fin to form at least an nFET group of fins having at least two fins and a pFET group of fins having at least one fin;
filling space between the fins with a shallow trench isolator (STI);
lowering a top of the STI to reveal the nFET and pFET groups of fins;
forming a nitride spacer layer over the STI and the nFET and pFET groups of fins, the nitride spacer layer having thickness equal to a fin distance between adjacent fins in the nFET group;
removing the nitride spacer layer that is further than the fin distance away from outer fins of the nFET group;
filling the spaces between remaining portions of the nitride spacer layer with additional STI;
removing the remaining portions of the nitride spacer layer to form first and second epi wells separated by a barrier formed by the additional STI;
forming a gate over the nFET and pFET groups of fins;
epitaxially growing source and drain contacts on either side of the gate in the first epi well; and
epitaxially growing source and drain contacts on either side of the gate in the second epi well;
wherein the barrier prevents the epitaxially grown source and drain contacts in the first epi well from contacting the epitaxially grown source and drain contacts in the second epi well.

11. The method of claim 10 , wherein forming the fins includes:
forming a fin hardmask on top of the substrate;
performing a reactive ion etching (REI) process on the substrate to remove portions of the substrate not covered by the fin hardmask.

12. The method of claim 11 , wherein removing the nitride spacer layer includes removing the fin hardmask.

13. The method of claim 10 , further comprising:
after the filling space between the fins with the shallow trench isolator (STI), performing a chemical-mechanical planarization (CMP) to level the STI and the fin hardmask.

14. The method of claim 13 , wherein a top of the epi wells is higher than a top of fins in the nFET and pFET groups.

15. The method of claim 10 , wherein the source and drains contacts in the first epi well are diamond shaped.

16. The method of claim 15 , wherein each of the fins in the first group has a diamond shaped source contact grown thereon and each of the diamond shaped contacts is in contact with an adjacent contact.

Assignees

• IBM

Inventors

• Cheng Kangguo
• Li Juntao
• Xu Peng

Classifications

• H10P95/06

  Planarisation of inorganic insulating materials · CPC title

• H10P50/692

  characterised by their composition, e.g. multilayer masks or materials · CPC title

• H10P50/242

  of Group IV materials · CPC title

• H01L29/0653

  Electricity · mapped topic

• H01L21/3081

  Electricity · mapped topic