Package structure having a plurality of conductive balls having narrow width for the ball waist

Patent metadata

Field	Value
Publication number	US-10276481-B2
Application number	US-201715798416-A
Country	US
Kind code	B2
Filing date	Oct 31, 2017
Priority date	Jun 26, 2017
Publication date	Apr 30, 2019
Grant date	Apr 30, 2019

Abstract

A package structure including a circuit substrate, a semiconductor die, a redistribution layer, a plurality of conductive balls and a circuit substrate is provided. The redistribution layer is disposed on the semiconductor die, and being electrically connected to the semiconductor die. The plurality of conductive balls is disposed between the redistribution layer and the circuit substrate. The semiconductor die is electrically connected to the circuit substrate through the conductive balls. Each of the conductive balls has a ball foot with a first width D 1 , a ball head with a third width D 3 and a ball waist with a second width D 2 located between the ball foot and the ball head. The ball foot is connected to the redistribution layer, the ball head is connected to the circuit substrate, and the ball waist is the narrowest portion of each of the conductive balls.

First claim

What is claimed is:

1. A package structure, comprising:
a circuit substrate having conductive pads;
a semiconductor die;
a redistribution layer, disposed on the semiconductor die, and being electrically connected to the semiconductor die; and
a plurality of conductive balls disposed between the redistribution layer and the circuit substrate, wherein the semiconductor die is electrically connected to the circuit substrate through the conductive balls, each of the conductive balls has a ball foot with a first width D 1 , a ball head with a third width D 3 and a ball waist with a second width D 2 located between the ball foot and the ball head, and wherein the ball foot is connected to the redistribution layer, the ball head is connected to the conductive pads of the circuit substrate, the ball waist is the narrowest portion of each of the conductive balls, and sidewalls of the ball foot extend beyond a lateral dimension of the conductive pads of the circuit substrate.

2. The package structure according to claim 1 , wherein the plurality of the conductive balls has a calabash shape, the ball foot and the ball head are barrel shaped with the ball waist located in-between.

3. The package structure according to claim 1 , wherein each of the conductive balls satisfies the relationship of D 3 >D 1 >D 2 , and a ratio of D 1 :D 2 :D 3 is in a range from 1.1:1.0:1.5 to 1.2:1.1:1.25.

4. The package structure according to claim 1 , wherein each of the conductive balls satisfies the relationship of D 1 ≥D 3 ≥D 2 , and a ratio of D 1 :D 2 :D 3 is in a range of 1.1:1.0:1.0 to 1.2:1.1:1.1.

5. The package structure according to claim 1 , further comprising:
an upholding layer located on the redistribution layer, wherein the upholding layer surrounds and partially covers the plurality of conductive balls.

6. The package structure according to claim 5 , wherein a height of the upholding layer is about half of a height of the plurality of the conductive balls.

7. The package structure according to claim 5 , wherein the upholding layer covers sidewalls of the ball foot and the ball waist.

8. The package structure according to claim 7 , wherein sidewalls of the ball head are exposed from the upholding layer.

9. A package structure, comprising:
an encapsulated semiconductor die;
a redistribution layer disposed on the encapsulated semiconductor die;
conductive balls disposed on the redistribution layer, wherein each of the conductive balls has a first terminal having curved sidewalls, a second terminal having sidewalls, and a ball waist between the curved sidewalls of the first terminal and the sidewalls of the second terminal, the first terminal is between the redistribution layer and the ball waist, and the ball waist is the narrowest portion of each of the conductive balls;
a circuit substrate having conductive pads, the circuit substrate is disposed on the plurality of conductive balls and being electrically connected to the redistribution layer through the conductive balls, wherein the second terminal is between the ball waist and the circuit substrate, and the curved sidewalls of the first terminal extend beyond a lateral dimension of the conductive pads of the circuit substrate; and
an upholding layer located on the redistribution layer, wherein an upper surface of the upholding layer is leveled with the ball waist, the upholding layer surrounds and partially covers the conductive balls, an air gap exist in between an upper surface of the upholding layer and a top surface of the circuit substrate, and the sidewalls of the second terminal are exposed from the upholding layer and exposed to the air gap.

10. The package structure according to claim 9 , wherein the plurality of the conductive balls has a calabash shape, the first terminal and the second terminal are barrel shaped with the ball waist located in-between.

11. The package structure according to claim 9 , wherein the first terminal has a first width D 1 , the ball waist has a second width D 2 , and the second terminal has a third width D 3 , each of the conductive balls satisfies the relationship of D 3 >D 1 >D 2 , and a ratio of D 1 :D 2 :D 3 is in a range from 1.1:1.0:1.5 to 1.2:1.1:1.25.

12. The package structure according to claim 9 , wherein the first terminal has a first width D 1 , the ball waist has a second width D 2 , and the second terminal has a third width D 3 , each of the conductive balls satisfies the relationship of D 1 >D 3 ≥D 2 , and a ratio of D 1 :D 2 :D 3 is in a range of 1.1:1.0:1.0 to 1.2:1.1:1.1.

13. The package structure according to claim 9 , wherein a height of the upholding layer is about half of a height of the plurality of conductive balls.

14. The package structure according to claim 9 , wherein the upholding layer covers the curved sidewalls of the first terminal.

15. A method of fabricating a package structure, comprising:
providing a semiconductor die;
forming a redistribution layer on the semiconductor die;
disposing a plurality of first conductive portions on the redistribution layer;
performing a partial melting process to partially melt the plurality of first conductive portions;
forming an upholding layer after the partial melting process to partially cover the first conductive portions;
providing a circuit substrate and a plurality of second conductive portions on the plurality of first conductive portions, wherein the plurality of second conductive portions is located in between the circuit substrate and the plurality of first conductive portions; and
joining the plurality of the second conductive portions with the plurality of the first conductive portions to form a plurality of conductive balls by performing a reflow process, wherein the circuit substrate is electrically connected to the redistribution layer through the plurality of conductive balls.

16. The method according to claim 15 , wherein joining the plurality of the second conductive portions with the plurality of the first conductive portions to form the plurality of conductive balls comprises forming ball waists of the plurality of the conductive balls at an interface where the plurality of the second conductive portions is joined with the plurality of the first conductive portions.

17. The method according to claim 16 , wherein the plurality of the first conductive portions form the ball foots of the plurality of the conductive balls, the second conductive portions form the ball heads of the plurality of the conductive balls.

18. The method according to claim 15 , wherein a height of the upholding layer is about half of a height of each of the conductive balls.

19. The method according to claim 15 , further comprising:
wherein the partial melting process is performed at a same temperature range as the reflow process.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chang Pi-Lan
• Chen Chen-Shien
• Ku Chin-Yu
• Chen Hsu-Hsien
• Huang Wei-Chih
• Lin Chun-Ying
• Chou Li-Chieh

Classifications

• H10W74/117

  the substrate having spherical bumps for external connection · CPC title

• H10W74/019

  using temporary auxiliary substrates (H10W74/017 takes precedence) · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W74/129

  forming a chip-scale package [CSP] · CPC title