Enhanced WLP for superior temp cycling, drop test and high current applications

US9099345B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9099345-B2
Application numberUS-201213608555-A
CountryUS
Kind codeB2
Filing dateSep 10, 2012
Priority dateMar 17, 2010
Publication dateAug 4, 2015
Grant dateAug 4, 2015

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A WLP device is provided with a flange shaped UBM or an embedded partial solder ball UBM on top of a copper post style circuit connection.

First claim

Opening claim text (preview).

What is claimed is: 1. A wafer level package (WLP) bump structure comprising: a copper pillar extending perpendicularly a first distance from a fabricated WLP silicon surface, the copper pillar comprising pillar sides and a distal portion that is distal from the fabricated WLP silicon surface, the distal portion comprising a copper surface; an encapsulant about the pillar sides and substantially covering the fabricated WLP silicon surface, the copper surface being recessed a fir…

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Frequently asked questions

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What does patent US9099345B2 cover?
A WLP device is provided with a flange shaped UBM or an embedded partial solder ball UBM on top of a copper post style circuit connection.
Who is the assignee on this patent?
Alvarado Rey, Wang Tie, Samoilov Arkadii, and 1 more
What technology area does this patent fall under?
Primary CPC classification H10W72/20. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 04 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).