Semiconductor device

Patent metadata

Field	Value
Publication number	US-10263117-B2
Application number	US-201514601625-A
Country	US
Kind code	B2
Filing date	Jan 21, 2015
Priority date	Jan 24, 2014
Publication date	Apr 16, 2019
Grant date	Apr 16, 2019

Abstract

A semiconductor device having favorable electric characteristics is provided. An oxide semiconductor layer includes first and second regions apart from each other, a third region which is between the first and second regions and overlaps with a gate electrode layer with a gate insulating film provided therebetween, a fourth region between the first and third regions, and a fifth region between the second and third regions. A source electrode layer includes first and second conductive layers. A drain electrode layer includes third and fourth conductive layers. The first conductive layer is formed only over the first region. The second conductive layer is in contact with an insulating layer, the first conductive layer, and the first region. The third conductive layer is formed only over the second region. The fourth conductive layer is in contact with the insulating layer, the third conductive layer, and the second region.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first insulating layer;
an oxide semiconductor layer over the first insulating layer;
a gate insulating layer over the oxide semiconductor layer;
a gate electrode over the gate insulating layer;
a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer electrically connected to the oxide semiconductor layer; and
a second insulating layer over and in contact with each of the second conductive layer, the fourth conductive layer, the gate electrode and a top surface of the oxide semiconductor layer,
wherein the oxide semiconductor layer includes a first region, a second region, a third region, a fourth region and a fifth region,
wherein the first region and the second region are apart from each other, the third region is between the first region and the second region, the third region and the gate electrode overlap with each other, the fourth region is between the first region and the third region, and the fifth region is between the second region and the third region,
wherein the first conductive layer is over and in direct contact with the first region,
wherein the second conductive layer covers the first insulating layer, a side surface of the first region, a top surface of the first conductive layer, and a side surface of the first conductive layer,
wherein the second conductive layer is in direct contact with each of the first insulating layer, the side surface of the first region, the top surface of the first conductive layer, and the side surface of the first conductive layer,
wherein the third conductive layer is over and in direct contact with the second region,
wherein the fourth conductive layer covers the first insulating layer, a side surface of the second region, a top surface of the third conductive layer, a side surface of the third conductive layer, and
wherein the fourth conductive layer is in direct contact with each of the first insulating layer, the side surface of the second region, the top surface of the third conductive layer, and the side surface of the third conductive layer.

2. The semiconductor device according to claim 1 , wherein the first conductive layer and the second conductive layer are configured to a source electrode, and the third conductive layer and the fourth conductive layer are configured to a drain electrode.

3. The semiconductor device according to claim 1 , further comprising a back gate electrode below the first insulating layer.

4. The semiconductor device according to claim 1 , wherein the oxide semiconductor layer is a stack including a first oxide semiconductor layer in contact with the first insulating layer, a second oxide semiconductor layer over the first oxide semiconductor layer, and a third oxide semiconductor layer over the second oxide semiconductor layer.

5. The semiconductor device according to claim 4 ,
wherein the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer each contain In, Zn, and M (M is Al, Ti, Ga, Y, Zr, La, Ce, Nd, or Hf), and
wherein the proportion of M with respect to In in the atomic ratio in each of the first oxide semiconductor layer and the third oxide semiconductor layer is higher than that in the second oxide semiconductor layer.

6. The semiconductor device according to claim 1 , wherein the oxide semiconductor layer contains a c-axis aligned crystal.

7. The semiconductor device according to claim 1 ,
wherein the fourth region and the fifth region each include a region in contact with the second insulating layer, and
wherein the second insulating layer is formed from a nitride insulating film containing hydrogen.

8. The semiconductor device according to claim 1 , wherein the fourth region and the fifth region each have a portion in which a concentration of one or more selected from phosphorus, arsenic, antimony, boron, aluminum, silicon, nitrogen, helium, neon, argon, krypton, xenon, indium, fluorine, chlorine, titanium, zinc, and carbon is higher than that in the third region.

9. The semiconductor device according to claim 1 , wherein the first conductive layer is a single layer or a stacked layer containing a material selected from Al, Cr, Cu, Ta, Ti, Mo, W, Ni, Mn, Nd, and Sc, and an alloy containing any of these metal materials.

10. The semiconductor device according to claim 1 , wherein the second conductive layer is a single layer or a stacked layer containing a material selected from titanium nitride, tantalum nitride, gold, platinum, palladium, ruthenium, and an oxynitride semiconductor.

11. An electronic device comprising the semiconductor device according to claim 1 and a display device.

12. A semiconductor device comprising:
a first insulating layer;
a first oxide semiconductor layer in contact with the first insulating layer;
a second oxide semiconductor layer over the first oxide semiconductor layer;
a third oxide semiconductor layer over the second oxide semiconductor layer;
a gate insulating layer over the third oxide semiconductor layer;
a gate electrode over the gate insulating layer;
a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer electrically connected to the second oxide semiconductor layer; and
a second insulating layer over and in contact with each of the second conductive layer, the fourth conductive layer, the gate electrode and a top surface of the second oxide semiconductor layer,
wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer includes a first region, a second region, a third region, a fourth region and a fifth region,
wherein the first region and the second region are apart from each other, the third region is between the first region and the second region, the third region and the gate electrode overlap with each other, the fourth region is between the first region and the third region, and the fifth region is between the second region and the third region,
wherein the first conductive layer is over and in direct contact with the first region of the second oxide semiconductor layer,
wherein the second conductive layer covers each of the first insulating layer, a side surface of the first region of the first oxide semiconductor layer, a side surface of the first region of the second oxide semiconductor layer, a top surface of the first conductive layer, and a side surface of the first conductive layer,
wherein the second conductive layer is in direct contact with each of the first insulating layer, the side surface of the first region of the first oxide semiconductor layer, the side surface of the first region of the second oxide semiconductor layer, the top surface of the first conductive layer, and the side surface of the first conductive layer,
wherein the third conductive layer is over and in direct contact with the second region of the second oxide semiconductor layer,
wherein the fourth conductive layer covers each of the first insulating layer, a side surface of the second region of the first oxide semiconductor layer, a side surface of the second region of the second oxide semiconductor layer, a top surface of the third conductive layer, and a side surface of the third conductive layer, and
wherein the fourth conductive layer is in direct contact with each of the first insulating layer, the side surface of the second region of the first oxide semiconductor layer, the side surface of the second region of the second oxide semiconductor layer, the top surface of the third conductive layer, and the side surface of the third conductive layer.

Assignees

• Semiconductor Energy Lab

Inventors

• Ito Daigo
• Hanaoka Kazuya

Classifications

• H01L29/78648

  Electricity · mapped topic

• H01L29/78696

  Electricity · mapped topic

• H01L29/7869 Primary

  Electricity · mapped topic

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6734

  having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs · CPC title