Manufacturing method of semiconductor device

Patent metadata

Field	Value
Publication number	US-9837545-B2
Application number	US-201615044428-A
Country	US
Kind code	B2
Filing date	Feb 16, 2016
Priority date	Jun 10, 2011
Publication date	Dec 5, 2017
Grant date	Dec 5, 2017

Abstract

A transistor using an oxide semiconductor, which has good on-state characteristics is provided. A high-performance semiconductor device including the transistor capable of high-speed response and high-speed operation is provided. The transistor includes the oxide semiconductor film including a channel formation region and low-resistance regions in which a metal element and a dopant are included. The channel formation region is positioned between the low-resistance regions in the channel length direction. In a manufacturing method of the transistor, the metal element is added by heat treatment performed in the state where the oxide semiconductor film is in contact with a film including the metal element and the dopant is added through the film including the metal element by an implantation method so that the low resistance regions in which a metal element and a dopant are included are formed.

First claim

What is claimed is:

1. A semiconductor device comprising:
an oxide semiconductor layer comprising a first region, a second region, and a third region;
a gate electrode layer over the oxide semiconductor layer;
a side wall insulator on a side surface of the gate electrode layer; and
a nitride layer over the oxide semiconductor layer, the gate electrode layer and the side wall insulator,
wherein the nitride layer comprises a metal element,
wherein the second region is between the first region and the third region,
wherein the first region comprises a channel formation region,
wherein the channel formation region and the gate electrode layer overlap each other,
wherein the side wall insulator and the second region overlap each other,
wherein the second region comprises argon,
wherein the third region is in contact with the nitride layer,
wherein the third region comprises argon and the metal element,
wherein a resistance of the second region is lower than a resistance of the first region,
wherein a resistance of the third region is lower than the resistance of the second region, and
wherein a concentration of the metal element of the third region is higher than a concentration of the metal element of the channel formation region.

2. The semiconductor device according to claim 1 , further comprising an insulating layer,
wherein the oxide semiconductor layer is over and in contact with the insulating layer.

3. The semiconductor device according to claim 2 , wherein the insulating layer comprises silicon oxide.

4. The semiconductor device according to claim 1 , wherein the oxide semiconductor layer comprises indium.

5. The semiconductor device according to claim 1 , wherein the oxide semiconductor layer comprises indium, gallium and zinc.

6. The semiconductor device according to claim 1 , wherein the gate electrode layer comprises titanium.

7. The semiconductor device according to claim 1 , further comprising a single crystal semiconductor substrate,
wherein the oxide semiconductor layer is over the single crystal semiconductor substrate.

8. A semiconductor device comprising:
an oxide semiconductor layer comprising a first region, a second region, and a third region;
a gate electrode layer over the oxide semiconductor layer;
a side wall insulator on a side surface of the gate electrode layer;
a source electrode layer;
a drain electrode layer; and
a nitride layer over the oxide semiconductor layer, the gate electrode layer and the side wall insulator,
wherein the nitride layer comprises a metal element,
wherein the second region is between the first region and the third region,
wherein the first region comprises a channel formation region,
wherein the channel formation region and the gate electrode layer overlap each other,
wherein the side wall insulator and the second region overlap each other,
wherein the source electrode layer and the drain electrode layer are in contact with the third region,
wherein the second region comprises argon,
wherein the third region is in contact with the nitride layer,
wherein the third region comprises argon and the metal element,
wherein a resistance of the second region is lower than a resistance of the first region,
wherein a resistance of the third region is lower than the resistance of the second region, and
wherein a concentration of the metal element of the third region is higher than a concentration of the metal element of the channel formation region.

9. The semiconductor device according to claim 8 , further comprising an insulating layer,
wherein the oxide semiconductor layer is over and in contact with the insulating layer.

10. The semiconductor device according to claim 9 , wherein the insulating layer comprises silicon oxide.

11. The semiconductor device according to claim 8 , wherein the oxide semiconductor layer comprises indium.

12. The semiconductor device according to claim 8 , wherein the oxide semiconductor layer comprises indium, gallium and zinc.

13. The semiconductor device according to claim 8 , wherein the gate electrode layer comprises titanium.

14. The semiconductor device according to claim 8 , further comprising a single crystal semiconductor substrate,
wherein the oxide semiconductor layer is over the single crystal semiconductor substrate.

15. The semiconductor device according to claim 1 ,
wherein the metal element is one or more selected from aluminum, titanium, molybdenum, tungsten, hafnium, tantalum, lanthanum, barium, magnesium, zirconium, and nickel.

16. The semiconductor device according to claim 8 ,
wherein the metal element is one or more selected from aluminum, titanium, molybdenum, tungsten, hafnium, tantalum, lanthanum, barium, magnesium, zirconium, and nickel.

17. A semiconductor device comprising:
an oxide semiconductor layer comprising a first region, a second region, and a third region;
a gate electrode layer over the oxide semiconductor layer;
a side wall insulator on a side surface of the gate electrode layer; and
a nitride layer over the oxide semiconductor layer, the gate electrode layer and the side wall insulator,
wherein the nitride layer comprises a metal element,
wherein the first region comprises a channel formation region,
wherein the channel formation region and the gate electrode layer overlap each other,
wherein the side wall insulator and the second region overlap each other,
wherein the third region is in contact with the nitride layer,
wherein the third region comprises the metal element,
wherein a resistance of the third region is lower than a resistance of the first region and a resistance of the second region, and
wherein a concentration of the metal element of the third region is higher than a concentration of the metal element of the channel formation region.

18. The semiconductor device according to claim 17 , further comprising an electrode layer electrically connected to the third region.

19. The semiconductor device according to claim 17 ,
wherein the metal element is one or more selected from aluminum, titanium, molybdenum, tungsten, hafnium, tantalum, lanthanum, barium, magnesium, zirconium, and nickel.

Assignees

• Semiconductor Energy Lab

Inventors

• Koezuka Junichi
• Ohno Shinji
• Sato Yuichi
• Yamazaki Shunpei

Classifications

• H01L29/4908

  Electricity · mapped topic

• H01L29/78603

  Electricity · mapped topic

• H01L29/78618

  Electricity · mapped topic

• H01L29/24

  Electricity · mapped topic

• H01L29/7869 Primary

  Electricity · mapped topic