Semiconductor device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-9349752-B2
Application number	US-201414296837-A
Country	US
Kind code	B2
Filing date	Jun 5, 2014
Priority date	Jan 12, 2011
Publication date	May 24, 2016
Grant date	May 24, 2016

Abstract

A first oxide insulating film is formed over a substrate. After a first oxide semiconductor film is formed over the first oxide insulating film, heat treatment is performed, so that hydrogen contained in the first oxide semiconductor film is released and part of oxygen contained in the first oxide insulating film is diffused into the first oxide semiconductor film. Thus, a second oxide semiconductor film with reduced hydrogen concentration and reduced oxygen defect is formed. Then, the second oxide semiconductor film is selectively etched to form a third oxide semiconductor film, and a second oxide insulating film is formed. The second oxide insulating film is selectively etched and a protective film covering an end portion of the third oxide semiconductor film is formed. Then, a pair of electrodes, a gate insulating film, and a gate electrode are formed over the third oxide semiconductor film and the protective film.

First claim

What is claimed is:

1. A semiconductor device comprising:
an oxide semiconductor layer over an oxide insulating layer;
a protective layer covering an end portion of the oxide semiconductor layer, wherein the end portion of the oxide semiconductor layer comprises a side surface and a part of a top surface of the oxide semiconductor layer;
a first electrode in contact with a bottom surface of the oxide semiconductor layer;
a second electrode in contact with the top surface of the oxide semiconductor layer;
a gate insulating layer in direct contact with the top surface of the oxide semiconductor layer, the gate insulating layer being over the protective layer; and
a gate electrode overlapping with the oxide semiconductor layer with the gate insulating layer interposed therebetween.

2. The semiconductor device according to claim 1 , wherein the oxide semiconductor layer is a non-single-crystal layer including a c-axis-aligned crystalline region.

3. The semiconductor device according to claim 1 , wherein the oxide semiconductor layer includes a first oxide semiconductor region overlapping with the gate electrode, a pair of second oxide semiconductor regions between which the first oxide semiconductor region is sandwiched, and a pair of third oxide semiconductor regions which overlaps with the second electrode and between which the pair of second oxide semiconductor regions is sandwiched.

4. The semiconductor device according to claim 3 ,
wherein the first oxide semiconductor region is a channel region,
wherein the pair of second oxide semiconductor regions is electric-field relaxation regions, and
wherein the pair of third oxide semiconductor regions is a source and a drain region.

5. The semiconductor device according to claim 3 , wherein the pair of second oxide semiconductor regions includes at least one element selected from nitrogen, phosphorus, and arsenic at a concentration higher than or equal to 5×10 18 atoms/cm 3 and lower than or equal to 1×10 22 atoms/cm 3 .

6. The semiconductor device according to claim 3 , wherein the pair of second oxide semiconductor regions includes at least one dopant selected from hydrogen, helium, neon, argon, krypton, and xenon at a concentration higher than or equal to 5×10 18 atoms/cm 3 and lower than or equal to 1×10 22 atoms/cm 3 .

7. The semiconductor device according to claim 1 , wherein the oxide semiconductor layer includes at least one element selected from In, Ga, Sn, and Zn.

8. The semiconductor device according to claim 1 , wherein the oxide insulating layer is an oxide insulating layer from which part of oxygen is released by heat treatment.

9. The semiconductor device according to claim 1 , wherein the oxide insulating layer is an oxide insulating layer containing oxygen at a proportion exceeding a stoichiometric proportion.

10. The semiconductor device according to claim 1 , wherein the first electrode is in direct contact with the bottom surface of the oxide semiconductor layer and the second electrode is in direct contact with the top surface of the oxide semiconductor layer.

11. The semiconductor device according to claim 1 , wherein the gate insulating layer is in direct contact with top surfaces of the first electrode and the second electrode.

12. The semiconductor device according to claim 1 , wherein the first electrode and the second electrode are in direct contact with the protective layer.

13. The semiconductor device according to claim 1 ,
wherein the first electrode is one of a source electrode and a drain electrode, and
wherein the second electrode is the other of the source electrode and the drain electrode.

14. A semiconductor device comprising:
an oxide semiconductor layer over an oxide insulating layer;
a protective layer in direct contact with an end portion of the oxide semiconductor layer, wherein the end portion of the oxide semiconductor layer comprises a side surface and a part of a top surface of the oxide semiconductor layer;
a first electrode in contact with a bottom surface of the oxide semiconductor layer;
a second electrode in contact with the top surface of the oxide semiconductor layer;
a gate insulating layer in direct contact with the top surface of the oxide semiconductor layer, the gate insulating layer being over the protective layer; and
a gate electrode overlapping with the oxide semiconductor layer with the gate insulating layer interposed therebetween.

15. The semiconductor device according to claim 14 , wherein the oxide semiconductor layer is a non-single-crystal layer including a c-axis-aligned crystalline region.

16. The semiconductor device according to claim 14 , wherein the oxide semiconductor layer includes a first oxide semiconductor region overlapping with the gate electrode, a pair of second oxide semiconductor regions between which the first oxide semiconductor region is sandwiched, and a pair of third oxide semiconductor regions which overlaps with the second electrode and between which the pair of second oxide semiconductor regions is sandwiched.

17. The semiconductor device according to claim 16 ,
wherein the first oxide semiconductor region is a channel region,
wherein the pair of second oxide semiconductor regions is electric-field relaxation regions, and
wherein the pair of third oxide semiconductor regions is a source and a drain region.

18. The semiconductor device according to claim 16 , wherein the pair of second oxide semiconductor regions includes at least one element selected from nitrogen, phosphorus, and arsenic at a concentration higher than or equal to 5×10 18 atoms/cm 3 and lower than or equal to 1×10 22 atoms/cm 3 .

19. The semiconductor device according to claim 16 , wherein the pair of second oxide semiconductor regions includes at least one dopant selected from hydrogen, helium, neon, argon, krypton, and xenon at a concentration higher than or equal to 5×10 18 atoms/cm 3 and lower than or equal to 1×10 22 atoms/cm 3 .

20. The semiconductor device according to claim 14 , wherein the oxide semiconductor layer includes at least one element selected from In, Ga, Sn, and Zn.

21. The semiconductor device according to claim 14 , wherein the oxide insulating layer is an oxide insulating layer from which part of oxygen is released by heat treatment.

22. The semiconductor device according to claim 14 , wherein the oxide insulating layer is an oxide insulating layer containing oxygen at a proportion exceeding a stoichiometric proportion.

23. The semiconductor device according to claim 14 , wherein the first electrode is in direct contact with the bottom surface of the oxide semiconductor layer and the second electrode is in direct contact with the top surface of the oxide semiconductor layer.

24. The semiconductor device according to claim 14 , wherein the gate insulating layer is in direct contact with top surfaces of the first electrode and the second electrode.

25. The semiconductor device according to claim 14 , wherein the first electrode and the second electrode are in direct contact with the protective layer.

26. The semiconductor device according to claim 14 ,
wherein the first electrode is one of a source electrode and a drain electrode, and
wherein the second electrode is the other of the source electrode and the drain electrode.

Assignees

• Semiconductor Energy Lab

Inventors

• Yamazaki Shunpei

Classifications

• H10D30/6704

  having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device · CPC title

• H10D30/031

  of thin-film transistors [TFT] · CPC title

• H10D30/6729

  characterised by the electrodes · CPC title

• H10D30/6755 Primary

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title

• H10D99/00

  Subject matter not provided for in other groups of this subclass · CPC title