Connection arrangements for integrated lateral diffusion field effect transistors

Patent metadata

Field	Value
Publication number	US-10249759-B2
Application number	US-201815899911-A
Country	US
Kind code	B2
Filing date	Feb 20, 2018
Priority date	Feb 20, 2017
Publication date	Apr 2, 2019
Grant date	Apr 2, 2019

Abstract

In an active layer over a semiconductor substrate, a semiconductor device has a first lateral diffusion field effect transistor (LDFET) that includes a source, a drain, and a gate, and a second LDFET that includes a source, a drain, and a gate. The source of the first LDFET and the drain of the second LDFET are electrically connected to a common node. A first front-side contact and a second front-side contact are formed over the active layer, and a substrate contact electrically connected to the semiconductor substrate is formed. Each of the first front-side contact, the second front-side contact, and the substrate contact is electrically connected to a different respective one of the drain of the first LDFET, the source of the second LDFET, and the common node.

First claim

The invention claimed is:

1. A semiconductor device, comprising:
a semiconductor substrate supporting an overlying active layer;
a first lateral diffusion field effect transistor (LDFET) in the active layer and comprising a source, a drain, and a gate;
a second LDFET in the active layer and comprising a source, a drain, and a gate;
a common node electrically and physically connected to the source of the first LDFET and the drain of the second LDFET;
a first front-side contact over the active layer and electrically and physically connected to a first one of: the drain of the first LDFET, the source of the second LDFET, and the common node;
a second front-side contact over the active layer and electrically and physically connected to a second one of: the drain of the first LDFET, the source of the second LDFET, and the common node;
a substrate contact electrically and physically connected to the semiconductor substrate and a third one of: the drain of the first LDFET, the source of the second LDFET, and the common node;
a buried dielectric layer between the semiconductor substrate and the active layer, wherein the substrate contact extends through the buried dielectric layer; and
a dielectric isolation barrier disposed between the first LDFET and the second LDFET and that extends through the active layer to the buried dielectric layer;
wherein each of the first front-side contact, the second front-side contact, and the substrate contact is electrically and physically connected to a different respective one of the drain of the first LDFET, the source of the second LDFET, and the common node.

2. The semiconductor device of claim 1 , wherein the buried dielectric layer extends under the source of the first LDFET, the drain of the first LDFET, the gate of the first LDFET, the source of the second LDFET, the drain of the second LDFET, and the gate of the second LDFET, a portion of the buried dielectric layer being omitted where the substrate contact intersects a plane of the buried dielectric layer.

3. The semiconductor device of claim 1 , wherein the substrate contact extends through the active layer.

4. The semiconductor device of claim 3 , wherein the substrate contact extends through one of the sources and drains of the first and second LDFETs.

5. The semiconductor device of claim 4 , wherein the substrate contact is electrically and physically connected to the common node.

6. The semiconductor device of claim 4 , wherein the substrate contact is electrically and physically connected to one of the first and second front-side contacts.

7. The semiconductor device of claim 3 , wherein the substrate contact comprises a first set of parallel substrate sub-contacts that are interleaved with a second set of parallel channel sub-contacts that are connected to one of the sources and drains of the first and second LDFETs, wherein the respective sub-contacts of the first and second sets extend to a surface above the active layer where they are alternately arranged in a row.

8. The semiconductor device of claim 3 , wherein the substrate contact extends through the active layer in a region free of any of the sources and drains of the first and second LDFETs, the region extending from a top surface of the active layer to a top surface of the semiconductor substrate, and the substrate contact is electrically and physically connected to one of the sources and drains of the first and second LDFETs by an electrical connection that extends laterally over the active layer and downward through one of the sources and drains of the first and second LDFETs.

9. The semiconductor device of claim 8 , wherein the substrate contact extends through an opening in the active layer that extends from the buried dielectric layer through the active layer.

10. The semiconductor device of claim 9 , wherein an edge-to-edge span of the substrate contact and an edge-to-edge span of the opening in the active layer have respective widths in a lateral dimension orthogonal to an axial dimension along which the substrate contact extends, and the width of the opening in the active layer is greater than the width of the substrate contact.

11. The semiconductor device of claim 3 , wherein the substrate contact extends through the active layer to the semiconductor substrate along an axial dimension, the substrate contact has a top portion that extends into the active layer, the top portion having an edge-to-edge span that is characterized by a first width in a lateral dimension orthogonal to the axial dimension, and the substrate contact has a bottom portion that extends into the active layer, the bottom portion having an edge-to-edge span that is characterized by a second width in the lateral dimension that is smaller than the first width.

12. The semiconductor device of claim 1 , further comprising a first electrically conductive clip and a second electrically conductive clip, wherein the first and second electrically conductive clips are electrically and physically connected to two of the first front-side contact, the second front-side contact, and the substrate contact.

13. The semiconductor device of claim 1 , further comprising a first electrically conductive clip electrically and physically connected to the first front-side contact and a second electrically conductive clip electrically and physically connected to the second front-side contact.

14. A semiconductor device, comprising:
a semiconductor substrate supporting an overlying active layer;
a first lateral diffusion field effect transistor (LDFET) in the active layer and comprising a source, a drain, and a gate;
a second LDFET in the active layer and comprising a source, a drain, and a gate, wherein the source of the first LDFET is electrically and physically coupled to the drain of the second LDFET;
a first front-side contact over the active layer and electrically and physically connected to the drain of the first LDFET;
a second front-side contact over the active layer and electrically and physically connected to the drain of the second LDFET and the source of the first LDFET;
a substrate contact electrically and physically connected to the semiconductor substrate and the source of the second LDFET;
a buried dielectric layer between the semiconductor substrate and the active layer, wherein the substrate contact extends through the buried dielectric layer; and
a dielectric isolation barrier disposed between the first LDFET and the second LDFET and that extends through the active layer to the buried dielectric layer.

15. The semiconductor device of claim 14 , wherein the buried dielectric layer extends under the source of the first LDFET, the drain of the first LDFET, the gate of the first LDFET, the source of the second LDFET, the drain of the second LDFET, and the gate of the second LDFET, a portion of the buried dielectric layer being omitted where the substrate contact intersects a plane of the buried dielectric layer.

16. A semiconductor device, comprising:
a semiconductor substrate supporting an overlying active layer;
a first lateral diffusion field effect transistor (LDFET) in the active layer and comprising a source, a drain, and a gate;
a second LDFET in the active layer and comprising a source, a drain, and a gate, wherein the drain of the first LDFET is electrically and physically coupled to the source of the second LDFET;
a first front-side contact over the active layer and electrically and physically connected to the source of the first LDFET;
a second front-side contact over the active layer and electrically and physically connected to the drain of the sec

Assignees

• Silanna Asia Pte Ltd

Inventors

• Tu Shanghui Larry
• Stuber Michael A
• Tasbas Befruz
• Molin Stuart B
• Jiang Raymond

Classifications

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W72/871

  Bond wires and strap connectors · CPC title

• H10W72/926

  Multiple bond pads having different sizes · CPC title

• H10W90/766

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/761

  of strap connectors · CPC title