Self-aligned air gap spacer for nanosheet CMOS devices

Patent metadata

Field	Value
Publication number	US-10243043-B2
Application number	US-201715811812-A
Country	US
Kind code	B2
Filing date	Nov 14, 2017
Priority date	Jun 12, 2017
Publication date	Mar 26, 2019
Grant date	Mar 26, 2019

Abstract

A semiconductor structure is provided that contains a plurality of vertically stacked and spaced apart semiconductor nanosheets in which an inner spacer liner and an air gap are present. Collectively, each inner spacer liner and air gap combination provides an inner spacer structure that separates a portion of a functional gate structure that surrounds each semiconductor nanosheet from a portion of a source/drain (S/D) semiconductor material structure that is present on each side of the functional gate structure.

First claim

What is claimed is:

1. A method of forming a semiconductor structure, the method comprising:
providing a fin stack of alternating layers of first semiconductor nanosheets and second semiconductor nanosheets located on a surface of a substrate, wherein a sacrificial gate structure and a gate spacer straddle over a portion of the fin stack;
recessing each first semiconductor nanosheet to provide a gap between each second semiconductor nanosheet;
forming an inner spacer liner in a portion of each gap and contacting a remaining portion of one of the first semiconductor nanosheets;
forming a source/drain (S/D) semiconductor material structure from each vertical end sidewall of each second semiconductor nanosheet, wherein during the forming of the source/drain (S/D) semiconductor material structures an air gap is formed between the inner spacer liner and each source/drain (S/D) semiconductor material structure; and
replacing the sacrificial gate structure and each remaining first semiconductor nanosheet with a functional gate structure.

2. The method of claim 1 , wherein each first semiconductor nanosheet comprises a first semiconductor material and each second semiconductor nanosheet comprises a second semiconductor material, wherein the first semiconductor material differs from the second semiconductor material and wherein the first semiconductor material can be removed selective to the second semiconductor material.

3. The method of claim 1 , wherein the recessing comprising:
thermally oxidizing end portions of each first semiconductor nanosheet to provide oxide end regions; and
removing each oxide end region.

4. The method of claim 1 , wherein the forming the inner spacer liner comprises:
forming an inner spacer material layer on physically exposed surfaces of the gate spacer, the sacrificial gate structure, the remaining portions of each first semiconductor nanosheet, each second semiconductor nanosheet and the substrate, and within a portion of each gap;
forming a dielectric material layer on the inner spacer material layer;
recessing the dielectric material layer, wherein a portion of the dielectric material layer remains on the inner spacer material layer that is located in each gap; and
removing the inner spacer material layer not protected by the remaining portion of the dielectric material layer in each gap.

5. The method of claim 4 , wherein the remaining portion of the dielectric material layer present in each gap remains.

6. The method of claim 4 , further comprising removing the remaining portion of the dielectric material layer prior to forming the source/drain (S/D) semiconductor material structures.

7. The method of claim 1 , wherein the replacing the sacrificial gate structure and each remaining first semiconductor nanosheet comprising:
forming a middle-of-the-line (MOL) dielectric material on each source/drain (S/D) semiconductor material structure, wherein the MOL dielectric material has a topmost surface that is coplanar with a topmost surface of the sacrificial gate structure; and
removing the sacrificial gate structure and each remaining first semiconductor nanosheet to provide a gate cavity; and
forming the functional gate structure in the gate cavity.

8. The method of claim 1 , wherein each second semiconductor nanosheet comprises silicon, and wherein each source/drain (S/D) semiconductor material structure is bounded to the vertical end sidewalls by <111> planes.

9. The method of claim 1 , wherein each inner spacer liner is C shaped and comprises a vertical portion, an upper horizontal portion and a lower horizontal portion.

Assignees

• IBM

Inventors

• Mochizuki Shogo
• Reznicek Alexander
• Rubin Joshua M
• Wang Junli

Classifications

• H01L29/66666

  Electricity · mapped topic

• H01L29/42356

  Electricity · mapped topic

• H01L29/7827

  Electricity · mapped topic

• H01L29/0649 Primary

  Electricity · mapped topic

• H01L29/045

  Electricity · mapped topic