Semiconductor device and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-2016190239-A1
Application number	US-201414583258-A
Country	US
Kind code	A1
Filing date	Dec 26, 2014
Priority date	Dec 26, 2014
Publication date	Jun 30, 2016
Grant date	—

Abstract

A semiconductor device is provided. The semiconductor device includes a sacrificial layer formed on a substrate, an active layer formed on the sacrificial layer, a gate insulating layer and a gate electrode formed to surround a part of the active layer, a spacer disposed on at least one side of the gate electrode, a source or drain separated from the gate electrode by the spacer and disposed on the substrate, and an air gap arrange between a lower portion of the active layer and the sacrificial layer, wherein the sacrificial layer is disposed on a lower portion of the source or drain and is not disposed on a lower portion of the gate electrode.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a sacrificial layer on a substrate; an active layer on the sacrificial layer; a gate insulating layer and a gate electrode surrounding a part of the active layer; a spacer disposed on at least one side of the gate electrode; a source or drain separated from the gate electrode by the spacer and disposed on the substrate; and an air gap disposed between a lower portion of the active layer and the sacrificial layer, wherein the sacrificial layer is disposed on a lower portion of the source or drain and is not disposed on a lower portion of the gate electrode.

2 . The semiconductor device of claim 1 , wherein the source or drain surrounds the active layer.

3 . The semiconductor device of claim 1 , wherein the height of the air gap is less than the height of the sacrificial layer, and
the height of the sacrificial layer is less than the height of the active layer.

4 . The semiconductor device of claim 3 , wherein the width of the air gap in a first direction is equal to the width of the gate electrode in the first direction.

5 . The semiconductor device of claim 1 , wherein the gate insulating layer is formed to completely surround the part of the active layer, and
the gate electrode is formed on an upper surface and both side surfaces of the part of the active layer, but is not formed on a lower surface thereof.

6 . The semiconductor device of claim 1 , wherein the sacrificial layer includes a first sacrificial layer and a second sacrificial layer positioned over the first sacrificial layer,
the active layer includes a first active layer positioned between the first sacrificial layer and the second sacrificial layer and a second active layer positioned on the second sacrificial layer, and the air gap includes a first air gap positioned between the first active layer and the substrate and a second air gap positioned between the first active layer and the second active layer.

7 . The semiconductor device of claim 1 , wherein the lower portion of the source or drain is disposed to be lower than the lower portion of the active layer, and
the active layer is not disposed on the lower portion of the source or drain.

8 . The semiconductor device of claim 7 , wherein the sacrificial layer includes a first sacrificial layer and a second sacrificial layer positioned on the first sacrificial layer,
the active layer includes a first active layer positioned between the first sacrificial layer and the second sacrificial layer and a second active layer positioned on the second sacrificial layer, and the air gap includes a first air gap positioned between the first active layer and the substrate and a second air gap positioned between the first active layer and the second active layer.

9 . The semiconductor device of claim 1 , wherein the gate electrode includes tungsten (W), and
the sacrificial layer is formed with a thickness of about 2 nm to about 4 nm.

10 . The semiconductor device of claim 1 , wherein the active layer and the sacrificial layer include a semiconductor material.

11 . The semiconductor device of claim 10 , wherein the active layer includes silicon (Si), and
the sacrificial layer includes silicon germanium (SiGe).

12 . The semiconductor device of claim 1 , further comprising a fin positioned on the substrate and positioned on a lower portion of the sacrificial layer,
wherein the air gap overlaps the fin.

13 . A semiconductor device comprising:
a substrate having a first region and a second region; a first nanowire transistor disposed on the first region; and a second nanowire transistor disposed on the second region, wherein the first nanowire transistor includes:
a first sacrificial layer formed on the substrate;
a first active layer formed on the first sacrificial layer;
a first gate electrode formed to surround a part of the first active layer; and
a first air gap formed between a lower portion of the first active layer and the first sacrificial layer, and
wherein the second nanowire transistor includes:
a second sacrificial layer formed on the substrate and including a material that is different from a material of the first sacrificial layer;
a second active layer formed on the second sacrificial layer;
a second gate electrode formed to surround a part of the second active layer; and
a second air gap formed between a lower portion of the second active layer and the second sacrificial layer.

14 . The semiconductor device of claim 13 , wherein the first sacrificial layer includes a semiconductor material,
the second sacrificial layer includes an insulating layer, the first nanowire transistor includes a PMOS transistor, and the second nanowire transistor includes an NMOS transistor.

15 . The semiconductor device of claim 13 , wherein the first nanowire transistor includes the first sacrificial layer, the first active layer, and the first air gap, and
the second nanowire transistor includes a plurality of the second sacrificial layers, a plurality of the second active layers, and a plurality of the second air gaps.

16 . A semiconductor device comprising:
a sacrificial layer on a substrate; an active layer on the sacrificial layer; a gate insulating layer completely surrounding a part of the active layer a gate electrode on the gate insulating layer; a spacer disposed on at least one side of the gate electrode; a source or drain separated from the gate electrode by the spacer and disposed on the substrate; and an air gap disposed between a lower portion of the active layer and the sacrificial layer, wherein the sacrificial layer is not disposed on a lower portion of the gate electrode.

17 . The semiconductor device of claim 16 , wherein a height of the air gap is less than a height of the sacrificial layer, and
the height of the sacrificial layer is less than a height of the active layer.

18 . The semiconductor device of claim 17 , wherein a width of the air gap in a first direction is equal to a width of the gate electrode in the first direction.

19 . The semiconductor device of claim 16 , wherein the sacrificial layer includes a first sacrificial layer and a second sacrificial layer positioned over the first sacrificial layer,
the active layer includes a first active layer positioned between the first sacrificial layer and the second sacrificial layer and a second active layer positioned on the second sacrificial layer, and the air gap includes a first air gap positioned between the first active layer and the substrate and a second air gap positioned between the first active layer and the second active layer.

20 . The semiconductor device of claim 16 , further comprising a fin positioned on the substrate and positioned on a lower portion of the sacrificial layer,
wherein the air gap overlaps the fin.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Suk Sung-Dae
• Seo Kang-Iii

Classifications

• H10D30/797

  being in source or drain regions, e.g. SiGe source or drain · CPC title

• H10D30/62 Primary

  Fin field-effect transistors [FinFET] · CPC title

• H10D86/215

  comprising FinFETs · CPC title

• H10D84/853

  comprising FinFETs · CPC title

• H10D84/0167

  Manufacturing their channels · CPC title