Processors, methods, and systems to access a set of registers as either a plurality of smaller registers or a combined larger register

Patent metadata

Field	Value
Publication number	US-10228941-B2
Application number	US-201313931047-A
Country	US
Kind code	B2
Filing date	Jun 28, 2013
Priority date	Jun 28, 2013
Publication date	Mar 12, 2019
Grant date	Mar 12, 2019

Abstract

A processor of an aspect includes a set of registers capable of storing packed data. An execution unit is coupled with the set of registers. The execution unit is to access the set of registers in at least two different ways in response to instructions. The at least two different ways include a first way in which the set of registers are to represent a plurality of N-bit registers. The at least two different ways also include a second way in which the set of registers are to represent a single register of at least 2N-bits. In one aspect, the at least 2N-bits is to be at least 256-bits.

First claim

What is claimed is:

1. A processor comprising:
a set of registers each capable of storing packed data;
a decode unit to decode instructions of an instruction set of the processor; and
an execution unit coupled with the set of registers, and coupled with the decode unit, the execution unit to access the set of registers in at least two different ways in response to the decoded instructions, the at least two different ways including:
a first way in which the set of registers are to represent a plurality of N-bit architectural registers, wherein at least one of the instructions of the instruction set has a field to explicitly specify any one of the plurality of N-bit architectural registers; and
a second way in which the set of registers are to represent a single architectural register of at least 2N-bits, and in which the at least 2N-bits is to be at least 256-bits.

2. The processor of claim 1 , in which in the second way the set of registers are to represent the single architectural register of 4N-bits, and in which the execution unit is also to access the set of registers in a third way in which the set of registers are to represent a plurality of 2N-bit architectural registers.

3. The processor of claim 2 , in which in the second way the set of registers are to represent the single architectural register which is to have at least 512-bits.

4. The processor of claim 1 , in which the execution unit is also to access the set of registers in a third way in which the set of registers are to represent a plurality of architectural N/2-bit registers.

5. The processor of claim 1 , in which in the first way the set of registers are to represent the plurality of 256-bit architectural registers and in the second way the set of registers are to represent the single architectural register of 512-bits.

6. The processor of claim 1 , in which in the second way the set of registers are to represent the single architectural register of at least 512-bits.

7. The processor of claim 1 , in which in the first way the set of registers are to represent the plurality of 128-bit architectural registers and in the second way the set of registers are to represent the single architectural register of 256-bits.

8. The processor of claim 1 , in which the execution unit is to be responsive to an instruction having an opcode to indicate a way in which the execution unit is to access the set of registers for that instruction.

9. The processor of claim 1 , in which the execution unit is to be responsive to an instruction having a field other than an opcode to indicate a way in which the execution unit is to access the set of registers for that instruction.

10. The processor of claim 1 , in which the processor comprises a reduced instruction set computing (RISC) processor, and in which the set of registers are N/2-bit registers.

11. The processor of claim 1 , in which the processor comprises a reduced instruction set computing (RISC) processor, and in which the set of registers are N-bit registers.

12. The processor of claim 1 , in which the execution unit is responsive to an instruction has one or more fields to specify the set of registers that in the second way are to represent the single architectural register.

13. A method performed by a processor comprising:
accessing a set of registers in a first way, in which the set of registers represent a plurality of N-bit architectural registers, to retrieve a corresponding N-bit packed data from each of the plurality of the N-bit architectural registers, wherein at least one instruction of an instruction set of the processor has a field to explicitly specify any one of the plurality of N-bit architectural registers; and
accessing the set of registers in a second way, in which the set of registers represent a single architectural register of at least 2N-bits, to retrieve a corresponding packed data of at least 2N-bits from the single architectural register, the at least 2N-bits being at least 256-bits, wherein at least one instruction of the instruction set of the processor has a field to explicitly specify the single architectural register of at least 2N-bits.

14. The method of claim 13 , in which accessing in the second way comprises accessing the set of registers that represent the single architectural register of 4N-bits, and further comprising accessing the set of registers in a third way in which the set of registers represent a plurality of 2N-bit architectural registers.

15. The method of claim 13 , in which accessing in the second way comprises accessing the set of registers that represent the single architectural register having at least 512-bits.

16. The method of claim 13 , further comprising accessing the set of registers in a third way in which the set of registers represent a plurality of N/2-bit architectural registers.

17. The method of claim 13 , in which accessing in the first way comprises accessing the set of registers which represent the plurality of 256-bit architectural registers, and in which accessing in the second way comprises accessing the set of registers which represent the single architectural register of 512-bits.

18. The method of claim 13 , in which accessing in the first way comprises accessing the set of registers which represent the plurality of 128-bit architectural registers, and in which accessing in the second way comprises accessing the set of registers which represent the single architectural register of 256-bits.

19. The method of claim 13 , in which accessing in the second way is responsive to an instruction having an opcode to indicate that the set of registers are to be accessed in the second way.

20. The method of claim 13 , in which accessing in the second way is responsive to an instruction having a field other than an opcode to indicate that the set of registers are to be accessed in the second way.

21. The method of claim 13 , in which accessing in the second way comprises accessing the set of registers that are N/2-bit registers.

22. A system to process instructions comprising:
an interconnect;
a processor coupled with the interconnect, the processor comprising:
a set of registers each able to store packed data;
an execution unit coupled with the set of registers, the execution unit to access the set of registers in at least three different ways in response to packed data instructions, the at least three different ways including:
a first way in which the set of registers are to represent a plurality of N-bit architectural registers to store packed data, wherein at least one packed data instruction of an instruction set of the processor has a field to explicitly specify any one of the plurality of N-bit architectural registers;
a second way in which the set of registers are to represent a single architectural register of at least 2N-bits to store packed data, wherein at least one packed data instruction of the instruction set of the processor has a field to explicitly specify the single architectural register of at least 2N-bits; and
a third way in which the set of registers are to represent a plurality of architectural registers having a width other than N-bits and less than the at least 2N-bits; and
a dynamic random access memory (DRAM) coupled with the interconnect.

23. The system of claim 22 , in which in the second way the set of registers are to represent the single architectural register of at least 256-bits.

24. An article of manufacture comprising a non-transi

Assignees

• Intel Corp

Inventors

• Toll Bret L
• Singhal Ronak
• Guy Buford M
• Naik Mishali

Classifications

• G06F9/30109

  having multiple operands in a single register · CPC title

• G06F9/30036 Primary

  Instructions to perform operations on packed data, e.g. vector, tile or matrix operations · CPC title

• G06F9/3016

  Decoding the operand specifier, e.g. specifier format · CPC title

• G06F9/30112

  comprising data of variable length · CPC title

• G06F9/30192

  according to data descriptor, e.g. dynamic data typing · CPC title