De-prioritizing speculative code lines in on-chip caches
US-12417182-B2 · Sep 16, 2025 · US
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Singhal Ronak patents
Singhal Ronak is listed as an inventor on 60 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Singhal Ronak |
| Total patents | 60 |
| First publication | Jan 1, 2015 |
| Latest publication | Sep 16, 2025 |
Notable patents
Publications ranked by popularity score, then publication date.
Systems, Apparatuses, and Methods for Resource Bandwidth Enforcement
US-2025217882-A1 · Jul 3, 2025 · US
Systems, apparatuses, and methods for resource bandwidth enforcement
US-12198186-B2 · Jan 14, 2025 · US
Apparatuses and methods for a processor architecture
US-12130740-B2 · Oct 29, 2024 · US
Packed data element predication processors, methods, systems, and instructions
US-12039336-B2 · Jul 16, 2024 · US
De-prioritizing speculative code lines in on-chip caches
US-2023185718-A1 · Jun 15, 2023 · US
Packed data element predication processors, methods, systems, and instructions
US-2023108016-A1 · Apr 6, 2023 · US
Packed data element predication processors, methods, systems, and instructions
US-11442734-B2 · Sep 13, 2022 · US
Apparatuses and methods for a processor architecture
US-2022237123-A1 · Jul 28, 2022 · US
Apparatuses and methods for a processor architecture
US-11294809-B2 · Apr 5, 2022 · US
Recent patents
Latest publications not already listed above.
Packed data element predication processors, methods, systems, and instructions
US-2021216325-A1 · Jul 15, 2021 · US
Monitoring the operation of a processor
US-11048588-B2 · Jun 29, 2021 · US
Packed data element predication processors, methods, systems, and instructions
US-10963257-B2 · Mar 30, 2021 · US
Monitoring the operation of a processor
US-2020257609-A1 · Aug 13, 2020 · US
Criticality based port scheduling
US-10719355-B2 · Jul 21, 2020 · US
Monitoring the operation of a processor
US-10599547-B2 · Mar 24, 2020 · US
Misprediction-triggered local history-based branch prediction
US-10579414-B2 · Mar 3, 2020 · US
Packed data element predication processors, methods, systems, and instructions
US-2020026518-A1 · Jan 23, 2020 · US
Efficient hardware-based extraction of program instructions for critical paths
US-10496413-B2 · Dec 3, 2019 · US
Packed data element predication processors, methods, systems, and instructions
US-10430193-B2 · Oct 1, 2019 · US
Criticality based port scheduling
US-2019243684-A1 · Aug 8, 2019 · US
Processors, methods, and systems to access a set of registers as either a plurality of smaller registers or a combined larger register
US-10228941-B2 · Mar 12, 2019 · US
Apparatuses and methods for a processor architecture
US-2019012266-A1 · Jan 10, 2019 · US
Multiple register memory access instructions, processors, methods, and systems
US-10170165-B2 · Jan 1, 2019 · US
Multiple register memory access instructions, processors, methods, and systems
US-10163468-B2 · Dec 25, 2018 · US
Multiple register memory access instructions, processors, methods, and systems
US-10153012-B2 · Dec 11, 2018 · US
Multiple register memory access instructions, processors, methods, and systems
US-10153011-B2 · Dec 11, 2018 · US
Method and apparatus for branch prediction utilizing primary and secondary branch predictors
US-2018349144-A1 · Dec 6, 2018 · US
Multiple register memory access instructions, processors, methods, and systems
US-10141033-B2 · Nov 27, 2018 · US
Multiple register memory access instructions, processors, methods, and systems
US-10102888-B2 · Oct 16, 2018 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Intel Corp | 53 |
| Lntel Corp | 7 |
| Singhal Ronak | 3 |
| Hinton Glenn J | 2 |
| Raasch Steven E | 2 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F9/30043 | 21 |
| G06F9/30109 | 20 |
| G11C7/1036 | 16 |
| G06F9/30163 | 16 |
| G06F9/30036 | 12 |