Methods, apparatus, instructions and logic to provide vector packed tuple cross-comparison functionality

Patent metadata

Field	Value
Publication number	US-2016188336-A1
Application number	US-201414588247-A
Country	US
Kind code	A1
Filing date	Dec 31, 2014
Priority date	Dec 31, 2014
Publication date	Jun 30, 2016
Grant date	—

Abstract

Instructions and logic provide SIMD vector packed tuple cross-comparison functionality. Some processor embodiments include first and second registers with a variable plurality of data fields, each of the data fields to store an element of a first data type. The processor executes a SIMD instruction for vector packed tuple cross-comparison in some embodiments, which for each data field of a portion of data fields in a tuple of the first register, compares its corresponding element with every element of a corresponding portion of data fields in a tuple of the second register and sets a mask bit corresponding to each element of the second register portion, in a bit-mask corresponding to each unmasked element of the corresponding first register portion, according to the corresponding comparison. In some embodiments bit-masks are shifted by corresponding elements in data fields of a third register. The comparison type is indicated by an immediate operand.

First claim

What is claimed is:

1 . A processor comprising:
a first vector register to store, in each of a plurality of n data fields, an element of a first data type; a second vector register or memory storage set to store, in each of a plurality of n data fields, a corresponding element of the first data type; a decode stage to decode a first instruction specifying a vector packed tuple cross-comparison operation and a tuple size; and one or more execution units, responsive to the decoded first instruction, to:
for each data field of a tuple-sized portion of said plurality of n data fields in the first vector register, compare its corresponding element with every element of a corresponding tuple-sized portion of the plurality of n data fields of said second vector register or memory storage set, and
set a mask bit corresponding to each element of said second vector register or memory storage set tuple-sized portion, in a bit-mask corresponding to each unmasked element of the corresponding first vector register tuple-sized portion, according to the corresponding comparison.

2 . The processor of claim 1 , wherein a type of comparison for the cross-comparison operation is indicated by an immediate operand specified by said first instruction.

3 . The processor of claim 2 , wherein a type of comparison for the cross-comparison operation is selected from the group consisting of: equal, less-than, less-than or equal, false, not equal, not less-than, not less-than or equal, and true.

4 . The processor of claim 1 , wherein the first instruction is a vector packed double compare instruction to cross-compare pairs of data fields of the first vector register with pairs of data fields of the second vector register or memory storage set.

5 . The processor of claim 1 , wherein the first instruction is a vector packed quadruple compare instruction to cross-compare four-tuples of data fields of the first vector register with four-tuples of data fields of the second vector register or memory storage set.

6 . The processor of claim 1 , wherein the first instruction is a vector packed octuple compare instruction to cross-compare eight-tuples of data fields of the first vector register with eight-tuples of data fields of the second vector register or memory storage set.

7 . The processor of claim 1 , wherein the plurality of n data fields is 64 data fields.

8 . The processor of claim 1 , wherein the plurality of n data fields is 32 data fields.

9 . The processor of claim 1 , wherein the plurality of n data fields is 16 data fields.

10 . The processor of claim 1 , wherein the plurality of n data fields is 8 data fields.

11 . The processor of claim 1 , wherein each of the plurality of n data fields of data fields is 8 bits.

12 . The processor of claim 1 , wherein each of the plurality of n data fields of data fields is 16 bits.

13 . The processor of claim 1 , wherein a number of mask bits set corresponding to each element of said second vector register or memory storage set tuple-sized portion comprises 2 bits.

14 . The processor of claim 1 , wherein a number of mask bits set corresponding to each element of said second vector register or memory storage set tuple-sized portion comprises 4 bits.

15 . The processor of claim 1 , wherein a number of mask bits set corresponding to each element of said second vector register or memory storage set tuple-sized portion comprises 8 bits.

16 . The processor of claim 1 , wherein the first instruction specifies a mask register operand having a bit to indicate whether each data field, respectively, of the plurality of n data fields in the first vector register is masked or unmasked.

17 . A method comprising:
storing in each of a plurality of n data fields of a first vector register, an element of a first data type; storing in each of a plurality of n data fields of a second vector register, a corresponding element of the first data type; executing, in a processor, a SIMD instruction for vector packed tuple cross-comparison; and for each data field of a portion of said plurality of n data fields in the first vector register, comparing its corresponding element with every element of a corresponding portion of the plurality of n data fields of the second vector register, and setting a mask bit corresponding to each element of the second register portion, in a bit-mask corresponding to each unmasked element of the corresponding first register portion, according to the corresponding comparison.

18 . The method of claim 17 , wherein each element of the first register is implicitly unmasked.

19 . The method of claim 17 , wherein n bits of a mask register are set to one or zero to explicitly indicate that a corresponding element of the first register is unmasked or masked respectively.

20 . The method of claim 17 , wherein the portion of said plurality of n data fields comprises two data fields.

21 . The method of claim 17 , wherein the portion of said plurality of n data fields comprises four data fields.

22 . The method of claim 17 , wherein the portion of said plurality of n data fields comprises eight data fields.

23 . A processing system comprising:
a memory; and a plurality of processors each processor comprising:
a first vector register to store, in each of a plurality of n data fields, an element of a first data type;
a second vector register or memory storage set to store, in each of a plurality of n data fields, a corresponding element of the first data type;
a decode stage to decode a first instruction specifying a vector packed tuple cross-comparison operation and a tuple size; and
one or more execution units, responsive to the decoded first instruction, to:
for each data field of a tuple-sized portion of said plurality of n data fields in the first vector register, compare its corresponding element with every element of a corresponding tuple-sized portion of the plurality of n data fields of said second vector register or memory storage set, and
set a mask bit corresponding to each element of said second vector register or memory storage set tuple-sized portion, in a bit-mask corresponding to each unmasked element of the corresponding first vector register tuple-sized portion, according to the corresponding comparison.

24 . The processing system of claim 23 , wherein a type of comparison for the cross-comparison operation is indicated by an immediate operand specified by said first instruction.

25 . The processing system of claim 23 , wherein a type of comparison for the cross-comparison operation is selected from the group consisting of: equal, less-than, less-than or equal, false, not equal, not less-than, not less-than or equal, and true.

26 . The processing system of claim 23 , wherein the first instruction is a vector packed double compare instruction to cross-compare pairs of data fields of the first vector register with pairs of data fields of the second vector register or memory storage set.

27 . The processing system of claim 23 , wherein the first instruction is a vector packed quadruple compare instruction to cross-compare four-tuples of data fields of the first vector register with four-tuples of data fields of the second vector register or memory storage set.

28 . The processing system of claim 23 , wherein the first instruction is a vector packed octuple compa

Assignees

• Intel Corp

Inventors

• Valentine Robert
• Hughes Christopher J
• Charney Mark J
• Sperber Zeev
• Gradstein Amit
• Rubanovich Simon
• Ould-Ahmed-Vall Elmoustapha
• Gebil Yuri

Classifications

• G06F9/3834

  Maintaining memory consistency · CPC title

• G06F9/30109

  having multiple operands in a single register · CPC title

• G06F9/30021 Primary

  Compare instructions, e.g. Greater-Than, Equal-To, MINMAX · CPC title

• G06F9/30043

  LOAD or STORE instructions; Clear instruction · CPC title

• G06F9/3838

  Dependency mechanisms, e.g. register scoreboarding · CPC title