Apparatuses and methods for a processor architecture
US-12130740-B2 · Oct 29, 2024 · US
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Guy Buford M patents
Guy Buford M is listed as an inventor on 21 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Guy Buford M |
| Total patents | 21 |
| First publication | Jan 1, 2015 |
| Latest publication | Oct 29, 2024 |
Notable patents
Publications ranked by popularity score, then publication date.
Packed data element predication processors, methods, systems, and instructions
US-12039336-B2 · Jul 16, 2024 · US
Packed data element predication processors, methods, systems, and instructions
US-2023108016-A1 · Apr 6, 2023 · US
Packed data element predication processors, methods, systems, and instructions
US-11442734-B2 · Sep 13, 2022 · US
Apparatuses and methods for a processor architecture
US-2022237123-A1 · Jul 28, 2022 · US
Apparatuses and methods for a processor architecture
US-11294809-B2 · Apr 5, 2022 · US
Packed data element predication processors, methods, systems, and instructions
US-2021216325-A1 · Jul 15, 2021 · US
Packed data element predication processors, methods, systems, and instructions
US-10963257-B2 · Mar 30, 2021 · US
Packed data element predication processors, methods, systems, and instructions
US-2020026518-A1 · Jan 23, 2020 · US
Packed data element predication processors, methods, systems, and instructions
US-10430193-B2 · Oct 1, 2019 · US
Recent patents
Latest publications not already listed above.
Zeroing a cache line
US-10282296-B2 · May 7, 2019 · US
Processors, methods, and systems to access a set of registers as either a plurality of smaller registers or a combined larger register
US-10228941-B2 · Mar 12, 2019 · US
Apparatuses and methods for a processor architecture
US-2019012266-A1 · Jan 10, 2019 · US
Packed data element predication processors, methods, systems, and instructions
US-2018293074-A1 · Oct 11, 2018 · US
Apparatuses and methods for a processor architecture
US-2018165199-A1 · Jun 14, 2018 · US
Packed data element predication processors, methods, systems, and instructions
US-9990202-B2 · Jun 5, 2018 · US
Processors, methods, and systems to implement partial register accesses with masked full register accesses
US-9934032-B2 · Apr 3, 2018 · US
Processors, methods, and systems to implement partial register accesses with masked full register accesses
US-2017109164-A1 · Apr 20, 2017 · US
Processors, methods, and systems to implement partial register accesses with masked full register accesses
US-9477467-B2 · Oct 25, 2016 · US
Processors, methods, and systems to access a set of registers as either a plurality of smaller registers or a combined larger register
US-2015006865-A1 · Jan 1, 2015 · US
Packed data element predication processors, methods, systems, and instructions
US-2015006858-A1 · Jan 1, 2015 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Intel Corp | 20 |
| Lntel Corp | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F9/30036 | 15 |
| G06F9/30038 | 15 |
| G06F9/30018 | 13 |
| G06F9/30189 | 10 |
| G06F12/0831 | 6 |