Operand size control

Patent metadata

Field	Value
Publication number	US-9804851-B2
Application number	US-201113064257-A
Country	US
Kind code	B2
Filing date	Mar 14, 2011
Priority date	Mar 15, 2010
Publication date	Oct 31, 2017
Grant date	Oct 31, 2017

Abstract

A data processing system is provided with processing circuitry as well as a bank of 64-bit registers. An instruction decoder decodes arithmetic instructions and logical instruction specifying arithmetic operations and logical operations to be performed upon operands stored within the 64-bit registers. The instruction decoder is responsive to an operand size field SF within the arithmetic instructions and the logical instructions specifying whether the operands are 64-bit operands or 32-bit operands where all of the operands are 64-bit operands or all of the operands are 32-bit operands. If a switch is made to a lower exception level, then a check is made as to whether or not a register being used was previously subject to a 64-bit write to that register. If such a 64-bit write had previously taken place, then the upper 32-bits are flushed so as to avoid data leakage from the higher exception level.

First claim

We claim:

1. An apparatus for processing data comprising:
a plurality of 2N-bit registers, each register configured to store only a single operand;
processing circuitry configured to perform data processing operations; and
instruction decoder circuitry, coupled to said processing circuitry and responsive to a stream of program instructions of only a fixed size of an instruction set, configured to generate control signals for controlling said processing circuitry to perform said data processing operations; wherein
said instruction decoder circuitry is configured to decode arithmetic instructions and logical instructions of said instruction set respectively specifying arithmetic operations and logical operations to be performed upon operands stored within said plurality of 2N-bit registers; and
said instruction decoder circuitry is configured to decode an operand size field within said arithmetic instructions and said logical instructions specifying only one of:
(i) said operands are 2N-bit operands each stored within a separate 2N-bit register of said plurality of 2N-bit registers; and
(ii) said operands are N-bit operands each stored within a separate 2N-bit register of said plurality of 2N-bit registers.

2. The apparatus as claimed in claim 1 , wherein all of said arithmetic instructions and all of said logical instructions within said instruction set include said operand size field.

3. The apparatus as claimed in claim 1 , wherein said operand size field specifies if an arithmetic operation or a logical operation to be performed is an 2N-bit processing operation to be performed upon 2N-bit operands or an N-bit processing operation to be performed upon N-bit operands.

4. The apparatus as claimed in claim 3 , comprising register renaming circuitry configured to provide a mapping between architectural registers specified within said program instructions and 2N-bit registers of said plurality of 2N-bit registers such that during operation said plurality of 2N-bit registers include one or more allocated registers currently mapped to said architectural registers and one or more unallocated registers not currently mapped to said architectural registers.

5. The apparatus as claimed in claim 4 , wherein said apparatus has a plurality of exception levels arranged in an exception level hierarchy.

6. The apparatus as claimed in claim 5 , wherein when a switch is made from a first exception level of said plurality of exception levels to a second exception level of said plurality of exception levels, with said second exception level being lower in said exception level hierarchy than said first exception level, said one or more unallocated registers are flushed so as to store predetermined values.

7. The apparatus as claimed in claim 5 , wherein when a switch is made from a first exception level of said plurality of exceptions to a second exception level of said plurality of exceptions, with said second exception level being lower in said level hierarchy than said first exception level, a dirty flag corresponding to each of said one or more unallocated registers is set.

8. The apparatus as claimed in claim 7 , wherein changing said 2N-bit register from being one of said one or more unallocated registers to being one of said one or more allocated registers, triggers bit positions within said 2N-bit register not overwritten with said N-bit value to be set to predetermined values.

9. The apparatus as claimed in claim 7 , wherein when a switch is made from a first exception level of said plurality of exception levels to a second exception level of said plurality of exception levels, with said second exception level being lower in said exception level hierarchy than said first exception level, said 2N-bit register having a set dirty flag is flushed so as to store a predetermined value.

10. The apparatus as claimed in claim 3 , wherein when said operand size field specifies an N-bit processing operation, a most significant N-bits within an 2N-bit register storing an N-bit result operand are one of:
(i) all set to zero; and
(ii) all set to a value sign extending said N-bit result operand.

11. The apparatus as claimed in claim 3 , wherein when said operand size field specifies an N-bit processing operation, a most significant N-bits within an 2N-bit register storing an N-bit result operand are not changed during said N-bit processing operation.

12. An apparatus for processing data comprising:
a plurality of 2N-bit register means for storing data values, each of said register means configured to store only a single operand;
processing means for performing data processing operations; and
instruction decoding means, coupled to said processing means, for generating control signals for controlling said processing means to perform said data processing operations in response to a stream of program instructions of only a fixed size of an instruction set; wherein
said instruction decoding means is configured to decode arithmetic instructions and logical instructions of said instruction set respectively specifying arithmetic operations and logical operations to be performed upon operands stored within said plurality of 2N-bit register means; and
said instruction decoding means is configured to decode an operand size field within said arithmetic instructions and said logical instructions specifying only one of:
(i) said operands are 2N-bit operands each stored within a separate 2N-bit register means of said plurality of 2N-bit register means; and
(ii) said operands are N-bit operands each stored within a separate 2N-bit register means of said plurality of 2N-bit register means.

13. A method of processing data comprising the steps of:
storing data values within a plurality of 2N-bit registers, each register configured to store only a single operand;
performing data processing operations using processing circuitry; and
decoding a stream of program instructions of only a fixed size of an instruction set to generate control signals for controlling said processing circuitry to perform said data processing operations; wherein
said decoding step decodes arithmetic instructions and logical instructions of said instruction set respectively specifying arithmetic operations and logical operations to be performed upon operands stored within said plurality of 2N-bit registers; and
said decoding decodes an operand size field within said arithmetic instructions and said logical instructions specifying only one of:
(i) said operands are 2N-bit operands each stored within a separate 2N-bit register of said plurality of 2N-bit registers; and
(ii) said operands are N-bit operands each stored within a separate 2N-bit register of said plurality of 2N-bit registers.

14. The method as claimed in claim 13 , wherein all of said arithmetic instructions and all of said logical instructions within said instruction set include said operand size field.

15. The method as claimed in claim 13 , wherein said operand size field specifies if an arithmetic operation or a logical operation to be performed is an 2N-bit processing operation to be performed upon 2N-bit operands or an N-bit processing operation to be performed upon N-bit operands.

16. The method as claimed in claim 15 , comprising mapping between architectural registers specified within said program instructions and 2N-bit registers of said plurality of 2N-bit registers such that during operation said plurality of 2N-bit registers include one or more allocated registers currently mapped to said architectural registers and one or more unallocated registers not currently mapped to sa

Assignees

• Grisenthwaite Richard Roy
• Seal David James
• Raphalen Philippe Jean-Pierre
• Smith Lee Douglas
• Advanced Risc Mach Ltd

Inventors

• Grisenthwaite Richard Roy
• Seal David James
• Raphalen Philippe Jean-Pierre
• Smith Lee Douglas

Classifications

• G06F9/30112

  comprising data of variable length · CPC title

• G06F9/3016 Primary

  Decoding the operand specifier, e.g. specifier format · CPC title

• G06F21/70

  Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer · CPC title

• G06F21/577

  Assessing vulnerabilities and evaluating computer system security · CPC title

• G06F9/3861

  Recovery, e.g. branch miss-prediction, exception handling (error detection or correction G06F11/00) · CPC title