Nitride structure having gold-free contact and methods for forming such structures

Patent metadata

Field	Value
Publication number	US-10224285-B2
Application number	US-201715438148-A
Country	US
Kind code	B2
Filing date	Feb 21, 2017
Priority date	Feb 21, 2017
Publication date	Mar 5, 2019
Grant date	Mar 5, 2019

Abstract

A semiconductor structure having a Group III-N semiconductor layer disposed on a substrate. A multi-layer, electrical contact structure in contact with the Group III-N semiconductor layer includes a gold-free contact layer in contact with the Group III-N semiconductor layer; and a gold-free electrically conductive etch stop layer electrically connected to the gold-free contact layer. An electrically conductive via passes through the substrate to the etch stop layer. The structure includes a plurality of electrode structures, each one providing a corresponding one of a source electrode structure, drain electrode structure and a gate electrode structure. The source electrode structure, drain electrode structure and gate electrode structure include: an electrical contact structure and an electrode contact. The electrode contacts have the same gold-free structure and have co-planar upper surfaces.

First claim

What is claimed is:

1. A semiconductor structure, comprising:
a substrate;
a Group III-N semiconductor structure disposed on the substrate;
a multi-layer, electrical contact structure in contact with the Group III-N semiconductor structure, the electrical contact structure comprising:
a gold-free contact layer in contact with the Group III-N semiconductor structure;
a gold-free electrically conductive etch stop layer disposed on with the gold-free contact layer and electrically connected to the gold-free contact layer; and,
a gold-free electrode contact in electrical contact with the gold-free electrically conductive etch stop layer;

an electrically conductive via passing through the substrate to gold-free electrically conductive etch stop layer, the gold-free electrically conductive etch stop layer having: a bottom surface in direct contact with an upper surface of the electrically conductive via; and an upper surface in direct contact with the gold-free electrode contact.

2. The semiconductor structure recited in claim 1 wherein an inner portion of the bottom surface of the gold-free electrically conductive etch stop layer is in contact with the electrically conductive via and an outer portion of the bottom surface of the gold-free electrically conductive etch stop is in contact with an outer portion of the gold-free contact layer.

3. The semiconductor structure recited in claim 1 wherein the gold-free contact layer comprises a metal silicide, the metal silicide being in Ohmic contact with the Group III-N semiconductor layer; and wherein the metal silicide is doped.

4. The semiconductor structure recited in claim 3 where the metal silicide is with Phosphorus (P), Arsenic (As), Antimony (Sb) or a combination thereof.

Assignees

• Raytheon Co

Inventors

• Laroche Jeffrey R
• Chumbes Eduardo M
• Ip Kelly P
• Kazior Thomas E

Classifications

• H10D64/257

  for lateral devices wherein the source or drain electrodes are characterised by top-view geometrical layouts, e.g. interdigitated, semi-circular, annular or L-shaped electrodes (source or drain electrodes of TFTs H10D30/673) · CPC title

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H10D64/254

  for lateral devices wherein the source or drain electrodes extend entirely through the semiconductor bodies, e.g. via-holes for back side contacts · CPC title

• H10W20/0242

  comprising etching via holes from the back sides of the chips, wafers or substrates · CPC title

• H10W20/0234

  comprising etching via holes that stop on pads or on electrodes · CPC title