Semiconductor device and method of manufacturing semiconductor device

Patent metadata

Field	Value
Publication number	US-9281370-B2
Application number	US-201414318064-A
Country	US
Kind code	B2
Filing date	Jun 27, 2014
Priority date	Jun 28, 2013
Publication date	Mar 8, 2016
Grant date	Mar 8, 2016

Abstract

A manufacturing method according to an embodiment of this invention is a method of manufacturing a semiconductor device, which has: a first step of forming a first electrode 22 containing Ti or Ta on a top face of a nitride semiconductor layer 18 ; a second step of forming a second electrode 24 containing Al on a top face of the first electrode 22 ; a third step of forming a coating metal layer 26 covering at least one of an edge of a top face of the second electrode 24 and a side face of the second electrode 24 , having a window 26 a exposing the top face of the second electrode 24 in a region separated from the foregoing edge, and containing at least one of Ta, Mo, Pd, Ni, and Ti; and a step of performing a thermal treatment, after the third step.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, comprising:
a first step of forming a first electrode containing Ti or Ta on a top face of a nitride semiconductor layer;
a second step of forming a second electrode containing Al on a top face of the first electrode;
a third step of forming a coating metal layer covering at least one of an edge of a top face of the second electrode and a side face of the second electrode, having a window exposing the top face of the second electrode in a region separated from the edge, and containing at least one of Ta, Mo, Pd, Ni, and Ti; and
a step of performing a thermal treatment, after the third step.

2. The method according to claim 1 , wherein a structure having the first electrode, the second electrode, and the coating metal layer constitutes at least one of a source electrode and a drain electrode arranged next to a gate electrode and wherein the coating metal layer is arranged on at least one of the edge of the top face of the second electrode and the side face of the second electrode on the side near to the gate electrode.

3. The method according to claim 1 , wherein the coating metal layer is provided on both of the edge of the top face of the second electrode and the side face of the second electrode.

4. The method according to claim 3 , wherein the coating metal layer covering the edge of the top face of the second electrode and the coating metal layer covering the side face of the second electrode are electrically connected.

5. The method according to claim 3 , wherein the coating metal layer covering the edge of the top face of the second electrode and the coating metal layer covering the side face of the second electrode are composed of an identical material.

6. The method according to claim 1 , wherein the nitride semiconductor layer is gallium nitride or aluminum gallium nitride and wherein the thermal treatment is carried out between 500° C. to 800° C.

7. The method according to claim 1 , wherein the coating metal layer provided on the side face of the second electrode is formed by carrying out anisotropic etching of the coating metal layer which formed on the second electrode.

Assignees

• Sedi Inc

Inventors

• Nishi Masahiro

Classifications

• H10P95/904

  of Group III-V semiconductors · CPC title

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10P50/264

  by chemical means · CPC title

• H10P14/2908

  Nitrides · CPC title